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[VHDL-FPGA-Verilog] anjian

Description: 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Platform: | Size: 2048 | Author: 汪汪 | Hits:

[matlab] CDMA_path_sim

Description: 该函数仿真CDMA系统的信道，在输入所需用户序列和其他干扰用户序列后在信号上叠加高斯白噪声，干扰用户多径干扰和所需用户的多径干扰和衰落。并根据输入延时曲线产生信道延时，输出mul_fad_sequence为信道信号输出，max_delay为信道最大延迟，fade_sign为瑞利信道中最大幅度分量的衰落量 mpath_amp为信道多径的幅度因子-the CDMA system simulation function of the channel, required users to import sequences and sequences of other users after the interference signal superimposed on the white Gaussian noise, Users interference and multi-path interference for users of multi-path interference and fading. Enter the delay under the curve Channel delay, mul_fad_sequence output of channel signal output, max_delay to channel the maximum delay, fade_sign Rayleigh Channel for the most significant component of the volume decline mpath_amp to channel more Drive rate factor
Platform: | Size: 2048 | Author: 刘洪 | Hits:

[VHDL-FPGA-Verilog] 9.1_ONE_PULSE

Description: 基于Verilog-HDL的硬件电路的实现 9.1 简单的可编程单脉冲发生器 　　9.1.1 由系统功能描述时序关系 　　9.1.2 流程图的设计 　　9.1.3 系统功能描述 　　9.1.4 逻辑框图 　　9.1.5 延时模块的详细描述及仿真 　　9.1.6 功能模块Verilog-HDL描述的模块化方法 　　9.1.7 输入检测模块的详细描述及仿真 　　9.1.8 计数模块的详细描述 　　9.1.9 可编程单脉冲发生器的系统仿真 　　9.1.10 可编程单脉冲发生器的硬件实现 　　9.1.11 关于电路设计中常用的几个有关名词 -based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Description logic diagram 9.1.5 9.1.4 Delay Module detailed description and simulation of 9.1. 6 functional modules Verilog-HDL description of the modular input method detection module 9.1.7 detailed 9.1.8 Description and Simulation module counting a detailed description 9.1.9 programmable pulse generator system 9.1.10 Simulation programmable pulse generator hardware on the circuit design 9.1.11 Constant Some of the terminology
Platform: | Size: 4096 | Author: 宁宁 | Hits:

[Embeded-SCM Develop] c_delay

Description: 几个精确C语言延时程序.1:500ms 2:200ms. 3:10ms.4:1s.-Several precision C language delay procedures .1:500 ms 2:200 ms.3: 10ms.4: 1s.
Platform: | Size: 1024 | Author: 张明 | Hits:

[Other] VC_Time_Delay

Description: VC延时函数汇总，内部附有非常详细的说明。-VC Delay aggregate function, the internal with a very detailed explanation.
Platform: | Size: 3072 | Author: 高一 | Hits:

[SCM] AVR-delayaccurate

Description: AVR128的毫秒和微秒级的精确延时程序。-AVR128 milliseconds and microseconds level of precision delay procedures.
Platform: | Size: 3072 | Author: zhangjing | Hits:

[assembly language] delay

Description: C51精确延时分析探讨 从精度考虑，它得研究结果是： void delay2(unsigned char i) { while(--i) } 为最佳方法。-C51 accurate analysis of delay from the accuracy considerations, it was the outcome of the study: void delay2 (unsigned char i) (while (i)) for the best way.
Platform: | Size: 1024 | Author: 向华 | Hits:

[SCM] msp430+1621

Description: 功能：用msp430驱动1621芯片的段码液晶 作者：徐世龙（网名：清风徐徐） 说明：源创（调试绝对能用） ---------------------------------------------------- cs-----p65 wr-----p64 dat----p63 mcu----msp430f135 ------------------------------------------------------------*/ /*------------------------ 功能：延时 参数：uint y 返回：无 说明：无 -------------------------*/ -Features: Driven by MSP430 Code Section 1621 chip LCD Authors:徐世龙(network name: Cheongpung slowly) Description: source of record (an absolute can debug) cs-p65 wr-p64 dat p63 mcu msp430f135*//* Function: Delay parameters : uint y return: None Description: No-* /
Platform: | Size: 1024 | Author: 第三代 | Hits:

[Embeded-SCM Develop] PIC-DELAY

Description: PIC汇编各个时间延时小程序，已经通过测试。总结~！-PIC compilation of various small time delay process, has passed the test. Summary ~!
Platform: | Size: 1024 | Author: zhangfulong | Hits:

[matlab] CDMAchannelsimulation(AWGN)

Description: 仿真CDMA系统的信道，在输入所需用户序列和其他干扰用户序列后在信号上叠加高斯白噪声，干扰用户多径干扰和所需用户的多径干扰和衰落。并根据输入延时曲线产生信道延时，输出mul_fad_sequence为信道信号输出，max_delay为信道最大延迟，fade_sign为瑞利信道中最大幅度分量的衰落量，mpath_amp为信道多径的幅度因子-Simulation of CDMA systems channel, the import requirements of the user sequence and other interference in the signal sequence users superimposed Gaussian white noise, multipath interference interference users and required the user s multipath interference and fading. And in accordance with input delay curve generated channel delay, the output for mul_fad_sequence signal output channel, max_delay to channel the maximum delay, fade_sign Rayleigh channel for the decline of the most significant amount of weight, mpath_amp for multipath channel magnitude factor
Platform: | Size: 2048 | Author: fisher | Hits:

[Communication-Mobile] Mean_64

Description: 原创代码，采用VHDL实现的64点均值滤波。实验测试过，效果良好。可轻松修改成任意点数均值滤波。采用了多点滑动运算，减小了输出延时，最大为3个时钟延迟。可用于AD采样后的滤波处理。-Original code, the use of VHDL to achieve the 64 point mean filter. Experiment tested the results were very good. Can be easily modified into arbitrary point mean filter. Use of multi-point sliding computation, reduces the output delay, a maximum of three clock delay. AD sampling can be used to deal with post-filtering.
Platform: | Size: 2048 | Author: M | Hits:

[VHDL-FPGA-Verilog] delay_line

Description: 延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module
Platform: | Size: 1024 | Author: zhangjing | Hits:

[VHDL-FPGA-Verilog] delay

Description: 用vhdl的状态机实现精确的1us的延时程序-VHDL state machine used to achieve precise 1us delay procedures
Platform: | Size: 1024 | Author: yim | Hits:

[SCM] Delay

Description: 关于ARM的延时, 实现方法： 用定时器的中断获得精确的延时-Delay for ARM
Platform: | Size: 1024 | Author: foryliu | Hits:

[SCM] delay

Description: 精确的c51延时程序，在c51环境下编写的精确的延时程序，绝对值得研究-accurate Programe of delay
Platform: | Size: 3072 | Author: 张乐天 | Hits:

[Other Embeded program] delay

Description: ARM的延时研究，给出了各种样式多方法，并对其中一种进行测试。-The ARM delay_study, the delay of research method, and the style of a test.
Platform: | Size: 2048 | Author: 刘丽辉 | Hits:

[VHDL-FPGA-Verilog] QuartusIIandModelSim

Description: 本文主要描述了如何在QUARTUS II 中输入程序文件，生成网表及标准延时文件，然后通过 MODELSIM进行功能仿真与后仿真的过程，主要为图解，含全部代码及仿真波形。 -This article describes how to enter at QUARTUS II program file, generate netlists and standard delay file, and then through the ModelSim for functional simulation and post-simulation process, mainly for the diagrams, containing all the code and the simulation waveform.
Platform: | Size: 277504 | Author: 朱雯 | Hits:

[Compress-Decompress algrithms] delay

Description: 一个可编程延时，只要输入你想的延时周期就可以延时几个周期-a program delay verilog
Platform: | Size: 17408 | Author: liaolain | Hits:

[VHDL-FPGA-Verilog] delay

Description: 短小易用的时序延迟程序，适用于Xilinx公司的FPGA产品-delay.vhd for Xilinx FPGA
Platform: | Size: 1024 | Author: xhnhd | Hits:

[SCM] delay

Description: 本代码是基于C8051f020单片机的时间延迟系统程序，主要实现功能是对生理信号的采集AD转换后，储存500MS的信号数据，然后经过DA转换输出，也可通过串口直接输出数字信号。实现延迟500MS模拟信号的作用-This code is based on the time delay C8051f020 SCM system program, the main feature is the collection of physiological signals after AD conversion, storage, 500MS signal data, and then through the DA converter output can also be directly output through the serial digital signal. Realize the role of the analog signal delay 500MS
Platform: | Size: 2048 | Author: zhangxibin | Hits:
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