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[matlab] Delta-Sigma调制器的仿真 DL : 0: 本Delta-Sigma调制器工具箱，包含了约100个函数，支持NTF综合，调制解调，实现，动态尺度调整，SNR估计等。
Update : 2010-10-13 Size : 555.71kb Publisher : 447537081@qq.com
[Other] cicmodule DL : 0: 一个3阶的CIC内插滤波器，可作为delta sigma DAC升采样率模块，用于半带滤波器后。-a three bands CIC interpolation filter, as delta sigma DAC sampling rate or module for the half-band filter.
Update : 2025-02-17 Size : 1kb Publisher : 老杜
[Other] 262-45526-LTC2453 DL : 0: Easy-to-Use, Ultra-Tiny, Differential, 16-Bit Delta Sigma ADC With I2C Interface The LTC2453 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter. The LTC2453 uses a single 2.7V to 5.5V supply and communicates through an I2C interface. The ADC is available in an 8-pin, 3mm x 2mm DFN package. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and has no latency for multiplexed applications. The LTC2453 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude lower than conventional delta-sigma converters. Additionally, due to its architecture, there is negligible current leakage between the input pins.
Update : 2025-02-17 Size : 267kb Publisher : Lee Ka Wing
[VHDL-FPGA-Verilog] FPGA-based-DAC DL : 1: 用fpga实现的DA转换器，有说明和源码，VDHL文件。 A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The simplest Delta-Sigma DAC consists of a Delta-Sigma modulator and a one bit DAC. Since, both of these components can be realized using digital circuits, it is possible to implement a low precision Delta-Sigma DAC using a PLD.-Using FPGA to achieve the DA converter, has descriptions and source code, VDHL document. A PLD Based Delta-Sigma DACDelta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinaryperformance and low cost of today s audio CDplayers. The simplest Delta-Sigma DAC consists of aDelta-Sigma modulator and a one bit DAC. Since , both of these components can be realized usingdigital circuits, it is possible to implement a lowprecision Delta-Sigma DAC using a PLD.
Update : 2025-02-17 Size : 57kb Publisher : 开心
[Embeded Linux] delsig DL : 0: Oversampling Delta-Sigma Data Converters
Update : 2025-02-17 Size : 533kb Publisher : 张海
[VHDL-FPGA-Verilog] 61EDA_D1116 DL : 0: A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The simplest Delta-Sigma DAC consists of a Delta-Sigma modulator and a one bit DAC. Since, both of these components can be realized using digital circuits, it is possible to implement a low precision Delta-Sigma DAC using a PLD. A better understanding of the Delta-Sigma DAC can-A PLD Based Delta-Sigma DAC
Update : 2025-02-17 Size : 58kb Publisher : 郭晨
[matlab] DSM DL : 0: delta sigma modulator
Update : 2025-02-17 Size : 2kb Publisher : nahid
[matlab] delsig DL : 0: MATLAB Delta Sigma developpement.
Update : 2025-02-17 Size : 739kb Publisher : nejmeddine
[Software Engineering] delta-segma DL : 0: Delta-sigma...simulink block-Delta-sigma...simulink block...
Update : 2025-02-17 Size : 18kb Publisher : suresh
[Books] Sigma_delta DL : 0: Delta-Sigma转换器是采用超采样的方法将模拟电压转换成数字量的1位转换器，它由1位ADC、１位DＡC与一个积分器组成，见图1。Delta-Sigma转换器的优点表现在低成本与高分辨率，适合用于现在的低电压半导体工业的生产-Delta-Sigma converters are super-sampling method to convert the analog voltage of a digital converter, which consists of an ADC, 1 Wei DAC with an integrator component, shown in Figure 1. Delta-Sigma converter performance advantages of low-cost and high-resolution, suitable for use in the current production of low-voltage semiconductor industry
Update : 2025-02-17 Size : 114kb Publisher : sherry
[Special Effects] ADC DL : 0: 该matlab程序验证了信号处理中delta-sigma ADC的效果，在过采样和delta-sigma单次循环后得到的图象性噪比提高。-The matlab program verification of signal processing in the effect of delta-sigma ADC, and the over-sampling delta-sigma a single image obtained after cycles of noise ratio increased.
Update : 2025-02-17 Size : 1kb Publisher : 王奇
[Communication] simulateDSM DL : 0: Compute the output of a general delta-sigma modulator with input u, a structure described by ABCD, an initial state x0 (default zero) and a quantizer with a number of levels specified by nlev. Multiple quantizers are implied by making nlev an array, and multiple inputs are implied by the number of rows in u. Alternatively, the modulator may be described by an NTF. The NTF is zpk object. (The STF is assumed to be 1.)
Update : 2025-02-17 Size : 2kb Publisher : hamdi
[matlab] simulateQSNR DL : 0: Determine the SNR for a quadrature delta-sigma modulator using simulations. The modulator is described by a noise transfer function (ntf) and the number of quantizer levels (nlev). The ntf/stf may be given in ABCD form. The band of interest is defined by the oversampling ratio (R) and the center frequency (f0).
Update : 2025-02-17 Size : 1kb Publisher : hamdi
[matlab] simulateSNR DL : 0: Determine the SNR for a delta-sigma modulator by using simulations. The modulator is described by a noise transfer function (ntf) and the number of quantizer levels (nlev).
Update : 2025-02-17 Size : 2kb Publisher : hamdi
[VHDL-FPGA-Verilog] delta-sigma DL : 1: 关于delta-sigma调制器的详细教程
Update : 2025-02-17 Size : 261kb Publisher : dsahd
[matlab] Multibit-Sigma-Delta-Modulator DL : 0: 一个经典的宽带多位sigma delta调制器设计，较为好用-More than a classic sigma delta modulator broadband design, the more useful
Update : 2025-02-17 Size : 936kb Publisher : 李兴
[matlab] Delta-Sigma DL : 1: Delta-Sigma (Σ-Δ)模数转换技术-Delta-Sigma (Σ-Δ) ADC
Update : 2025-02-17 Size : 648kb Publisher : hehe
[VHDL-FPGA-Verilog] decimator DL : 0: Digital filter in delta-sigma ADC. But only work for RTL code now. Still have bugs in gate-level simulation.
Update : 2025-02-17 Size : 1kb Publisher : DrCheese
[VHDL-FPGA-Verilog] A-FPGA-Based-Delta-Sigma-DAC DL : 0: 用FPGA实现AD转换的代码,使用VHDL语言编写-A FPGA Based Delta-Sigma DAC
Update : 2025-02-17 Size : 58kb Publisher : wang
[VHDL-FPGA-Verilog] delta-sigma DL : 1: 实现了MASH111功能，输入位数可编程(MASH 1-1-1, delta-sigma , input bits are programmable)
Update : 2025-02-17 Size : 1.44mb Publisher : alieng

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