Description: 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation. Platform: |
Size: 8747 |
Author:sarahyu |
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Description: 双端口RAM的VHDL语言实现。完全在CPLD芯片上测试通过。可以实现对存储器读操作的同时对另外一个空间写操作-dual-port RAM VHDL. Totally CPLD chip test. Memory can be achieved right time to operate while the other was a space operation Platform: |
Size: 90112 |
Author:王雪松 |
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Description: 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation. Platform: |
Size: 8192 |
Author:sarahyu |
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Description: 用EDA设计ROM和RAM及其应用，用VHDL语言编程实现字符、汉字的存取并用点阵显示-ROM and RAM design with the EDA and its applications, using VHDL programming language characters, Chinese characters, access to and use dot-matrix display Platform: |
Size: 13039616 |
Author:黄奇家 |
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Description:
This file with the wavelet transf
Mallat implementation of wavelet
Verilog hdl code modules for radi
Modelsim 6.6 crack, can be used f
A written using Verilog DDR2 cont
Simple CPU VHDL implementation an
Dual-port RAM design, using Veril
Verilog language, a hardware-base
FPGA embedded project combat, Man
Application FPGA, FPGA-chip hardw
Mallat implementation of wavelet
Layer of one-dimensional wavelet Platform: |
Size: 1852416 |
Author:sansfroid |
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Description: 本文介绍了应用FPGA实现对高速A/D转换芯片的控制电路，介绍了这一控制的设计思想，并提出了通过双口RAM实现FPGA与慢速度的单片机进行双机数据通信处理的解决方案。- Data acquisition is an item of indispensable technology which is essential to the industrial control system. As the increasing need for speed performance of the data collection requirements, FPGA technology came into being. This paper introduces the high-speed A/D converter by using FPGA chip control circuit detailing, discussing the design of the control circuit, at the same time submitting the FPGA through dual-port RAM and slow-speed single-chip dual-computer data communications solutions. FPGA and Single-chip microcomputer mutual coordination work, control the data acquisition system, and Single-chip microcomputer with rich peripherals can be extended accordingly. The circuit of the design that use VHDL language to complete. Through the program designing and testing, the voltage information which is showed in the PC through serial port transmission collected ultimately. It is successful to realize the mutual communication between FPGA and single-chip microcomputer. Platform: |
Size: 117760 |
Author:陈建华 |
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Description: 用VHDL语言设计一个8位双向可控移位寄存器。
移位寄存器由D型触发器构成，采用串入并出形式。
采用VHDL方式设计一个16х4位RAM存储器-VHDL language to design an 8-bit bidirectional shift register controllable. The shift register by a D-type flip-flops, using the string into and out of form. Way design using VHDL a bit RAM memory 16х4 Platform: |
Size: 1024 |
Author:赵丽丽 |
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Search - design RAM using VHDL