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[VHDL-FPGA-Verilog] DS_FH

Description: 扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现-Frequency-hopping communication QUARTUS7.0 expanded development environment in the VHDL source code and the achievement of the overall block diagram
Platform: | Size: 2278400 | Author: Rebecca | Hits:

[Voice Compress] yuyintongxin

Description: 基于CPLD的语音通信系统设计与实现毕业设计 原版包括程序源码，各部分仿真图，框图-CPLD-based voice communications system design and implementation of the design of the original graduate program, including source code, the part of simulation diagram, block diagram
Platform: | Size: 3988480 | Author: 李卫东 | Hits:

[Other] FPGA-DDC

Description: 基于DSPbuilder的数字变频文章，有simulink方框图-Based on the number of frequency DSPbuilder articles, there are simulink block diagram
Platform: | Size: 5936128 | Author: 小聪 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
Platform: | Size: 15360 | Author: 张霄 | Hits:

[Other] led

Description: 七段LED数码显示器是数字系统中常用的数码显示元件，二进制数不能直接在LED数码管上显示，需要用一个BCD七段译码器进行译码。下图给出了一个七段显示译码器的框图及相应的七段LED数码管的示意图。-Seven-segment LED digital display is commonly used in digital systems digital display devices, a binary number can not be directly displayed on the LED digital tube, needed a seven-segment BCD decoder for decoding. The following figure shows a block diagram of seven-segment display decoder and the corresponding seven-segment LED digital tube schematic.
Platform: | Size: 29696 | Author: 乐天猫 | Hits:

[Other] trafic

Description: 交通管理器的VHDL设计，简单实用，包括了语言和模块图-Traffic Manager of the VHDL design, simple and practical, including the language and block diagram
Platform: | Size: 104448 | Author: cheng | Hits:

[VHDL-FPGA-Verilog] FULLTEXT01

Description: this a program that contains the vhdl m file and vhdl code for the hole block diagram system-this is a program that contains the vhdl m file and vhdl code for the hole block diagram system
Platform: | Size: 562176 | Author: kareem | Hits:

[VHDL-FPGA-Verilog] RS232_FIR

Description: Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
Platform: | Size: 202752 | Author: jay | Hits:

[VHDL-FPGA-Verilog] vhdl-implementation-of-cordic-algorithm-for-wirel

Description: OFDM system model and Block diagram of CORDIC algorithm using FPGA VHDL code -OFDM system model and Block diagram of CORDIC algorithm using FPGA VHDL code
Platform: | Size: 395264 | Author: | Hits:

[Software Engineering] FPGA-based-frequency-counter

Description: 文章主要介绍了使用VHDL实现数字频率计的功能，其中包含了各部件的VHDL语言描述，仿真和大致硬件框图，对于初学EDA者大有帮助。-The article introduces the VHDL realization of the functionality of the digital frequency meter, which contains the hardware block diagram of the various components of the VHDL language description, simulation and approximate, and is a great help for beginners EDA.
Platform: | Size: 777216 | Author: 金刚 | Hits:

[File Format] dianliuyuanMSP430F5419

Description: 这是基于MSP430F5419单片机的直流电流源设计的报告，有程序和原理框图，quartus vhdl,希望帮到大家-This report is based on the the MSP430F5419 MCU DC current source design, procedures and schematic block diagram of the Quartus vhdl, we hope to help
Platform: | Size: 590848 | Author: 伍 | Hits:

[VHDL-FPGA-Verilog] myfpga

Description: 详细描述设计过程 ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义） ⑦ 实验总结，在调试和下载过程中遇到的问题 -Design Process Design ② ① instruction format defined micro-operation ③ ④ processor division beat a detailed description of the structural design and function block diagram (score focus) a detailed description single wire connection between modules with thin lines, 2 and above with crude line and mark the number and. b. Use the arrow indicating the flow of data, signal names used in cases of functional modules shall be marked ⑤ structural design diagram and functional description (score focus) ⑥ VHDL code on connection, UCF file test instruction sequence (the meaning of each instruction) ⑦ experiments summarized in debugging and downloading problems encountered in the process
Platform: | Size: 6259712 | Author: 王思雨 | Hits:

[VHDL-FPGA-Verilog] lab6

Description: 详细描述设计过程和实验中遇到的问题，包括： ① 指令格式设计 ② 微操作的定义 ③ 节拍的划分 ④ 处理器详细结构设计框图及功能描述(评分重点) a. 模块之间的连线单线用细线，2根及以上用粗线并标出根数及. b. 用箭头标明数据流向,例化时用到的信号名称应标在连线上 ⑤ 各功能模块结构设计框图及功能描述（评分重点） ⑥ VHDL代码、UCF文件、测试指令序列（每条指令的含义） 实验总结，在调试和下载过程中遇到的问题 -A detailed description of the design process and problems encountered in the experiment, including:. ① ② micro-operation instruction format design definition ③ ④ processor division beat detailed description of the structural design and function block diagram (score focus) a single-wire connection between modules with a thin, two more than the number indicated by bold lines and and. b. Use the arrow indicating the flow of data, signal names used when instantiated ⑤ shall be marked on the connection of each functional module design and function block diagram and description (Ratings Key) ⑥ VHDL code, UCF file, test instruction sequence (the meaning of each instruction) experiments summarized problems encountered during commissioning and download the
Platform: | Size: 5848064 | Author: 王思雨 | Hits:

[Other] Quartus

Description: Quartus II完全教程 内部资料 提供了完全集成且与电路结构无关的开发包环境，具有数字逻辑设计的全部特性，包括： 可利用原理图、结构框图、VerilogHDL、AHDL和VHDL完成电路描述，并将其保存为设计实体文件；芯片（电路）平面布局连线编辑等-Quartus II complete tutorial provides a fully integrated internal data and independent of the circuit structure of the development package environment, with all the characteristics of digital logic design, including: Available schematics, block diagram, VerilogHDL, AHDL and VHDL complete circuit description, and save it as a design entity files chip (circuit) connection layout editing
Platform: | Size: 7505920 | Author: 刘欣 | Hits:

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