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[Other resource] add_sub_lab2

Description: 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
Platform: | Size: 60734 | Author: 徐轶尊 | Hits:

[VHDL-FPGA-Verilog] 多个Verilog的代码

Description: 多个VHDL编码的例题，详细的电路图介绍，还有流程图-many examples of VHDL code, the particular introduction of circuit diagram and flow chart
Platform: | Size: 88064 | Author: 陈栋栋 | Hits:

[VHDL-FPGA-Verilog] add_sub_lab2

Description: 实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。-experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
Platform: | Size: 60416 | Author: 徐轶尊 | Hits:

[Other] lattice

Description: Lattice 公 司 把 当 今 两 种 最 新 的 系 统 设 计 技 术，VHDL 和 在 系 统 可 编 程 ( ISP ) 逻 辑 器 件 联 系 在 一 起， 构 成 了isp-VHDl Viewlogic 系 统。isp-VHDL 是 进 行 电 子 系 统 设 计 的 强 有 力 的 工 具， 使 用 它 可 以 加 快 设 计 产 品 投 放 市 场 的 时 间。 isp-VHDL Viewlogic 软 件 能 用 于 各 种 逻 辑 设 计， 这 套 软 件 具 有 功 能 强 大 的 VHDL 综 合、原 理 图 输 入、功 能 与 时 序 仿 真、ispDS+ 适 配 器 和 ispDOWNLOAD 能 力。-two companies today the latest design technology, VHDL and in-system programmable (ISP) logic device linked constitute a isp- VHDl Viewlogic Systems. Isp-VHDL is an electronic system designed powerful tool, It can be used to speed up the design of products on the market in time. Isp-VHDL Viewlogic software can be used for various logic design, This software has powerful VHDL synthesis, diagram entry, functional and timing simulation, ispDS adapter and ispDOWNLOAD capacity.
Platform: | Size: 507904 | Author: kurt | Hits:

[VHDL-FPGA-Verilog] VHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642816 | Author: Jawen | Hits:

[Embeded-SCM Develop] RTL8019ASEthernet

Description: 这是一个以太网接口RTL8019AS和电路图一份．希望对大家有点参考-This is a RTL8019AS Ethernet interface and a circuit diagram. We hope that a bit of reference
Platform: | Size: 21504 | Author: 蔡再来 | Hits:

[SCM] zuihoudeyanjiu

Description: 步进电机控制，控制器,控制电机的VHDL源程序,,多平台 Digital_030423.rar - 服务器的的板在载控制器的AHDL程序,包括原理图编译,用-stepper motor control, controllers, motor control VHDL source files, and Multi-platform Digital_030423.rar-server contains the controller board in the tap procedure , including diagram compiler, and
Platform: | Size: 17408 | Author: | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] ddschengxu

Description: dds程序 有原理图 代码 哈哈 dds程序 有原理图 代码 -dds procedures diagram code says dds procedures diagram code
Platform: | Size: 22528 | Author: | Hits:

[File Format] te3560

Description: 基于VHDL语言的实用电梯控制器的设计 -based on VHDL practical elevator controller design based on VHDL practical Elevator Controller VHDL design based on the practical design of the elevator controller based on VHDL practical elevator controller design
Platform: | Size: 94208 | Author: | Hits:

[Embeded-SCM Develop] vhdlshiyan

Description: 本文为采用VHDL编写的程序及报告。步骤如下：1设计三位二进制计数器程序 二:设计一驱动循环显示7位数字 2编写LED控制程序如下： 3设计采用原理图方式如下: -VHDL paper prepared for the introduction of procedures and reports. Steps are as follows : Design of a binary counter three two procedures : Design of a drive cycle show seven figures prepared two LED control procedures are as follows : three designs diagram as follows :
Platform: | Size: 296960 | Author: 梁兵 | Hits:

[VHDL-FPGA-Verilog] jiaotongdeng

Description: 交通灯VHDL设计，所有程序和顶层逻辑图都有，编译已通过，管脚分配可按实际分配-VHDL design of traffic lights, all the procedures and have a top-level logic diagram, the compiler has passed, according to the actual distribution of pin allocation
Platform: | Size: 234496 | Author: zhang | Hits:

[Embeded-SCM Develop] Interleave

Description: 在Maxplus软件平台开发的，使用原理图开发的fpga的纠错编码和交织以及解纠错和解交织的源码文件-In Maxplus software platform developed using the schematic diagram of the FPGA development of error-correcting coding and intertwined, as well as forward error correction solutions reconciliation of source documents interwoven
Platform: | Size: 4150272 | Author: 熊浩 | Hits:

[VHDL-FPGA-Verilog] elvator_control_base_on_fpga

Description: 这是一个使用VHDL语言设计的电梯控制程序，里面还有仿真时序图。-This is a design using the VHDL language elevator control procedures, along with simulation timing diagram.
Platform: | Size: 482304 | Author: 宝石 | Hits:

[assembly language] VHDLsiweichufaqi

Description: 这是一个利用MAX PULL 制作的VHDL的四位除法器的程序 如果有需要仿真图的 请叫站长联系我-This is a MAX PULL produced using VHDL divider of the four procedures, if necessary simulation diagram contact me please call station
Platform: | Size: 2048 | Author: 郭明磊 | Hits:

[assembly language] VHDLjianfaqi

Description: 这是一个利用MAX PULL 制作的VHDL的减法器的程序 如果有需要仿真图的 请叫站长联系我-This is a MAX PULL produced using VHDL s process of subtraction, if necessary simulation diagram contact me please call station
Platform: | Size: 1024 | Author: 郭明磊 | Hits:

[VHDL-FPGA-Verilog] alarm

Description: 1．6个数码管动态扫描显示驱动 2．按键模式选择(时\分\秒)与调整控制 3．用硬件描述语言(或混合原理图)设计时、分、秒计数器模块、按键控制状态机模块、动态扫描显示驱动模块、顶层模块。要求有闹钟定闹功能，时、分定闹即可，无需时、分、秒定闹。要求使用实验箱左下角的6个动态数码管(DS6 A~DS1A)显示时、分、秒；要求模式按键和调整按键信号都取自经过防抖处理后的按键跳线插孔。-1.6 Digital control of dynamic scanning display driver 2. Mode selection button (when minutes and seconds) and adjust the control 3. Using hardware description language (or a combination of schematic diagram) design, minute and second counter module, key control state machine module, dynamic scanning display driver module, the top-level module. Required to make the alarm set function, the sub-set can make without hour, minute, second set downtown. Require the use of lower-left corner of the experimental box 6 dynamic digital tube (DS6 A ~ DS1A) shows hours, minutes, seconds request mode button and adjust the signal from the button after button after the Anti-shake deal with jack jumper.
Platform: | Size: 621568 | Author: xulina | Hits:

[SCM] MyDesign

Description: protel99se下的数字示波器原理图及PCB图-Protel99SE under the digital oscilloscope and PCB schematic diagram
Platform: | Size: 84992 | Author: 王奎 | Hits:

[Other Embeded program] TimingDesigner

Description: IC领域的时序图作图软件，简单方便，英文版，无需注册，已经破解-IC timing diagram mapping the field of software, simple English, are not required to register, has been cracked
Platform: | Size: 3673088 | Author: JET | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
Platform: | Size: 15360 | Author: 张霄 | Hits:
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