Search - digilent

[Other resource] S3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731568 | Author: Roy Hsu | Hits:

[Graph program] quantizer

Description: 这个DCT的源代码Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA
Platform: | Size: 51397 | Author: lilei | Hits:

[Embeded-SCM Develop] verilog-clock

Description: 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Platform: | Size: 1024 | Author: 李瑞 | Hits:

[VHDL-FPGA-Verilog] S3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731136 | Author: Roy Hsu | Hits:

[Graph program] quantizer

Description: 这个DCT的源代码Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA-The DCT of source code Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA
Platform: | Size: 51200 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] pong

Description: Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.
Platform: | Size: 74752 | Author: wangfeng | Hits:

[VHDL-FPGA-Verilog] CPLD_Implementation_of_a_Lucky_Dip_Machine

Description: 摸奖桶程序设计也就是乐透彩票模拟程序程序为verilogHDL描述详细请看英文描述-Digital Electronic Design Automation Workshop on Rapid Prototyping using a CPLD Lucky Dip Machine using the Digilent X-Board
Platform: | Size: 4096 | Author: 吴德昊 | Hits:

[Other] 0470185325

Description: Good book on introduction to programming on Digilent Spartan FPGA board in Verilog by Pong Chu
Platform: | Size: 17115136 | Author: rax | Hits:

[VHDL-FPGA-Verilog] vga

Description: VGA interface using Spartan3E board from DIGILENT.Labview .vi
Platform: | Size: 143360 | Author: unu | Hits:

[VHDL-FPGA-Verilog] 4BCD

Description: 4个7段lcd同时显示的程序，已经在digilent的nexy2板上通过验证，非常好用易懂，适合初学者学习-display 4 leds
Platform: | Size: 3072 | Author: zhang fei | Hits:

[VHDL-FPGA-Verilog] calc_v2_s3eboard

Description: Simple calculator EDK design implemented on Digilent S3EBOARD using Microblaze soft-core CPU. Input: PS/2 keyboard, output: VGA monitor.
Platform: | Size: 2952192 | Author: madcrow | Hits:

[MultiLanguage] I2C_vdec1

Description: Comunicacion I2c para el video decodificador VDEC1 de Digilent
Platform: | Size: 5120 | Author: steephen13 | Hits:

[VHDL-FPGA-Verilog] vacantfiles

Description: VGA source code for Digilent Inc board Basys
Platform: | Size: 3072 | Author: Enticing Fury | Hits:

[VHDL-FPGA-Verilog] vacantfiles2

Description: digilent vga board files
Platform: | Size: 6144 | Author: Enticing Fury | Hits:

[VHDL-FPGA-Verilog] Tutorial09_Clock

Description: 基于Spartan-3e的数码管显示时钟程序的设计，整个流程讲解详细。-A very important concept in digital design is that of the clock. A clock is used to synchronize systems in digital logic, and provides a convenient way to keep track of real time. Another equally important fact is the ability to translate information to a human readable form. In our case, the peripheral module seven segment display device PmodSSD will be used. The Digilent Spartan 3E Starter board has a 50 MHz oscillator that is used creatively to obtain other useful clock frequencies.
Platform: | Size: 414720 | Author: 飞飞三号 | Hits:

[VHDL-FPGA-Verilog] Oscilloscope

Description: The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware. The circuits were designed on a Windows XP using the Xilinx WebPack 6.2 tool. The transfer of the design to the FPGA was carried out either with the Xilinx Impact tool through a parallel JTAG cable or with the Digilent Export utility through a USB JTAG cable.
Platform: | Size: 1854464 | Author: sami | Hits:

[Embeded-SCM Develop] w11_latest[1].tar

Description: 该项目包含一个完整的PDP - 11系统：一个内存管理单元七十○分之十一的CPU，但没有浮点单元，一组基本的单总线外围设备（DL11，LP11，PC11，RK11/RK05），以及最后但并非最不重要的一用于SRAM和PSRAM高速缓存和内存控制器。该设计的FPGA验证，目前运行Digilent的S3BOARD和NEXYS2板和靴子第5版的UNIX和2.11BSD UNIX操作系统。-The project contains a complete PDP-11 system: a 11/70 CPU with memory management unit, but without floating point unit, a basic set of UNIBUS peripherals (DL11, LP11, PC11, RK11/RK05), and last but not least a cache and memory controllers for SRAM and PSRAM. The design is FPGA proven, runs currently on Digilent S3BOARD and NEXYS2 boards and boots 5th Edition UNIX and 2.11BSD UNIX.
Platform: | Size: 714752 | Author: zhaohaiting | Hits:

[Other Embeded program] CEREBOT32MX4-LED-Demo

Description: Required Hardware • Digilent Cerebot 32MX4 • USB A to Micro-B Cable • Digilent Pmod8LD (optional)-Required Hardware • Digilent Cerebot 32MX4 • USB A to Micro-B Cable • Digilent Pmod8LD (optional)
Platform: | Size: 404480 | Author: 唐本风 | Hits:

[VHDL-FPGA-Verilog] Intro_to_Digital_Design-Digilent-Verilog_Online.r

Description: a course of design of vhdl-a course of design of vhdl
Platform: | Size: 4072448 | Author: salah | Hits:

[Other] Intro_to_Digital_Design-Digilent-Verilog_Online.r

Description: Intro to Digital Design Digilent Verilog Online
Platform: | Size: 4072448 | Author: Quan | Hits:

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[Other resource] S3Demo

[Graph program] quantizer

[Embeded-SCM Develop] verilog-clock

[VHDL-FPGA-Verilog] S3Demo

[Graph program] quantizer

[VHDL-FPGA-Verilog] pong

[VHDL-FPGA-Verilog] CPLD_Implementation_of_a_Lucky_Dip_Machine

[Other] 0470185325

[VHDL-FPGA-Verilog] vga

[VHDL-FPGA-Verilog] 4BCD

[VHDL-FPGA-Verilog] calc_v2_s3eboard

[MultiLanguage] I2C_vdec1

[VHDL-FPGA-Verilog] vacantfiles

[VHDL-FPGA-Verilog] vacantfiles2

[VHDL-FPGA-Verilog] Tutorial09_Clock

[VHDL-FPGA-Verilog] Oscilloscope

[Embeded-SCM Develop] w11_latest[1].tar

[Other Embeded program] CEREBOT32MX4-LED-Demo

[VHDL-FPGA-Verilog] Intro_to_Digital_Design-Digilent-Verilog_Online.r

[Other] Intro_to_Digital_Design-Digilent-Verilog_Online.r

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