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[VHDL-FPGA-VerilogTime

Description: ALTERA上DE2平台,利用内部50M Hz时钟,在数码管模拟显示时间(时分秒)。-ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).
Platform: | Size: 609280 | Author: 徐朝凯 | Hits:

[VHDL-FPGA-Verilog5b6b

Description: 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输,串行码序列中连续的比特0或比特1的长度不超过5,数据在0和1之间变换的密度很高,并具有直流平衡的特性,有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or bit 1 of the length of not more than 5, data between 0 and 1, the high density of transformation, and has the characteristics of DC balance, favorable reception circuit and clock recovery circuit.
Platform: | Size: 3072 | Author: 王彬 | Hits:

[Otherdigitalclock

Description: Verilog数字时钟 实现24小时的监控,用七段码显示出来,包含时序图等 在ISE下仿真-digital clock Verilog
Platform: | Size: 370688 | Author: 唐新明 | Hits:

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