Search - digital vhdl

[VHDL-FPGA-Verilog] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6633472 | Author: 穆群生 | Hits:

[VHDL-FPGA-Verilog] 分频器VHDL描述

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
Platform: | Size: 5120 | Author: 王力 | Hits:

[VHDL-FPGA-Verilog] muxplusii --vhdl 经典程序

Description: 用VHDL编写的数字时钟,可变宽度脉冲产生器-prepared using VHDL digital clock, Variable width pulse generator, etc.
Platform: | Size: 8192 | Author: vhdp | Hits:

[Software Engineering] digital_system-VHDL

Description: 数字系统与VHDL程序设计语言[PPT教程] ，非常有用． -Digital System Design with VHDL language [PPT Guide], very useful.
Platform: | Size: 932864 | Author: huangxi | Hits:

[Other] Verilog.HDL.A.Guide.To.Digital.Design.And.Synthesi

Description: VHDL的数字设计与综合的经典图书，与大家共享-VHDL digital design and synthesis of the classic books, and share
Platform: | Size: 1723392 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] fir-vhdl

Description: 用Vhdl硬件描述语言编写的FIR数字滤波器-Vhdl using Hardware Description Languages in preparing the FIR digital filter
Platform: | Size: 5120 | Author: MAX | Hits:

[Documents] VHDL

Description: VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Platform: | Size: 569344 | Author: yyy | Hits:

[VHDL-FPGA-Verilog] vhdl--timer

Description: 关于基于fpga的，数字化时钟vhdl实现源程序，推荐大家下载仿真实现。-On the FPGA-based, digital clock source VHDL realize recommend everyone to download simulation.
Platform: | Size: 6144 | Author: sxd | Hits:

[Books] VHDl

Description: VHDL数字控制系统设计范例，PDG格式的，希望对大家有用！-VHDL Examples of digital control system design, PDG format, in the hope that useful to everybody!
Platform: | Size: 6585344 | Author: gjd | Hits:

[VHDL-FPGA-Verilog] VHDLcode

Description: 一本很好的关于学习VHDL的书,Fundamentals of Digital Logic with VHDL Design,我的导师在教我VHDL时使用的教材.上传的是书内包含的所有的代码.-A good book on VHDL study, Fundamentals of Digital Logic with VHDL Design, my mentor, I teach the use of VHDL teaching materials. From the book contains all the code.
Platform: | Size: 107520 | Author: nan | Hits:

[Other] VHDL

Description: 东南大学电工电子实验中心徐莹隽老师的VHDL数字系统设计，对于VHDL的初学者非常适合。-Southeast University, Electrical and Electronic Experiment Center Jun Xu Ying teachers VHDL digital system design, the VHDL is well suited for beginners.
Platform: | Size: 1509376 | Author: 杨春山 | Hits:

[Embeded-SCM Develop] VHDL

Description: VHDL数字钟数字电子钟此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能；-VHDL digital clock digital clock digital electronic clock with this function include: 1. Time, hours, minutes and seconds display 2. 12 hours and 24 hours between the conversion 3. On the afternoon show 4. hours, minutes and seconds of the school function
Platform: | Size: 3072 | Author: HJGJGHK | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟有闹钟,秒表,时钟,日期等功能秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL硬件描述语言与数字逻辑电路设计——学习FPGA/CPLD时可参考-VHDL hardware description language and digital logic circuit design- to learn FPGA/CPLD can reference
Platform: | Size: 18691072 | Author: 陨星 | Hits:

[VHDL-FPGA-Verilog] taxi-vhdl

Description: 出租车计费器硬件描述语言出租车计费器 MAX+PLUS软件数字系统-Taxi billing hardware description language taxi meter MAX+ PLUS software digital systems
Platform: | Size: 48128 | Author: aneeee | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过-A direct digital frequency synthesis of look-up table procedures, VHDL language, using 7128 debugging through
Platform: | Size: 147456 | Author: Chen.Y.M | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 用VHDL实现数字频率计,1. 时基产生与测频时序控制电路模块2. 待测信号脉冲计数电路模块3.锁存与译码显示控制电路模块4.顶层电路模块. -Using VHDL digital frequency meter, 1. Time-base generation and frequency measurement timing control circuit module 2. Analyte signal pulse counting circuit module 3. Latch and decoding display control circuit module 4. Top-level circuit module.
Platform: | Size: 13312 | Author: 侯治强 | Hits:

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[VHDL-FPGA-Verilog] VHDL语言100例详解

[VHDL-FPGA-Verilog] 分频器VHDL描述

[VHDL-FPGA-Verilog] muxplusii --vhdl 经典程序

[Software Engineering] digital_system-VHDL

[Other] Verilog.HDL.A.Guide.To.Digital.Design.And.Synthesi

[VHDL-FPGA-Verilog] fir-vhdl

[Documents] VHDL

[VHDL-FPGA-Verilog] vhdl--timer

[Books] VHDl

[VHDL-FPGA-Verilog] VHDLcode

[Other] VHDL

[Embeded-SCM Develop] VHDL

[Software Engineering] clock

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] taxi-vhdl

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] VHDL

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