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[Other resource] DigitalClockVHDL DL : 0: 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
Update : 2008-10-13 Size : 82.63kb Publisher : wangyiran
[VHDL-FPGA-Verilog] DigitalClockVHDL DL : 0: 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
Update : 2025-02-17 Size : 82kb Publisher : wangyiran
[VHDL-FPGA-Verilog] digitalclockvhdl DL : 0: EAD设计VHDL语言环境数字时钟数码管显示方案，包括时间设置、调整等。-VHDL language environment EAD design digital digital clock display, including time for setup, adjustment.
Update : 2025-02-17 Size : 8kb Publisher : 王丽