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[Embeded-SCM Developdirital_clock_7

Description: verilog实现电子时钟模块,输入60Hz时钟信号和复位,输出时分秒,共6位,每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
Platform: | Size: 1116 | Author: seiji | Hits:

[Embeded-SCM Developdirital_clock_7

Description: verilog实现电子时钟模块,输入60Hz时钟信号和复位,输出时分秒,共6位,每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
Platform: | Size: 1024 | Author: | Hits:

[Embeded-SCM Developdirital_clock_7

Description: verilog实现电子时钟模块,输入60Hz时钟信号和复位,输出时分秒,共6位,每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
Platform: | Size: 1024 | Author: thefou | Hits:

[Embeded-SCM Developdirital_clock_7

Description: verilog实现电子时钟模块,输入60Hz时钟信号和复位,输出时分秒,共6位,每位7段输出用于驱动-verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
Platform: | Size: 1024 | Author: beunvei | Hits:

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