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Embeded-SCM Develop
Title:
dirital_clock_7
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Category:
Embeded-SCM Develop
Tags:
[VHDL]
[源码]
File Size:
1.09kb
Update:
2008-10-13
Downloads:
0 Times
Uploaded by:
Description:
verilog electronic clock module, 60Hz input clock signal and reset, Minutes exportation, a total of six, each of the seven drivers for output
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