Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: elc_clock Download
 Description: Verilog design practice elc_clock electronic clock
 To Search: elc_clock
  • [electronicbellclock] - use VHDL to achieve an electronic clock,
  • [dirital_clock_7] - verilog electronic clock module, 60Hz in
  • [dianzhishizhong] - electronic clock display system design e
  • [clock] - Written using Verilog HDL Digital Clock,
  • [tclk] - ALARM = 1 when called buzzer.- The first
  • [clock] - With electronic clock, stopwatch, alarm
  • [5] - Using VHDL language electronic bell
  • [clock] - VHDL-based design of an electronic clock
  • [shizhong] - From the VHDL code with other different,
File list (Check if you may need any files):
复件 电子时钟
.............\db
.............\..\add_sub_3dc.tdf
.............\..\add_sub_4dc.tdf
.............\..\add_sub_59c.tdf
.............\..\add_sub_5dc.tdf
.............\..\add_sub_6dc.tdf
.............\..\add_sub_7dc.tdf
.............\..\alt_u_div_4oe.tdf
.............\..\elc_clock.asm.qmsg
.............\..\elc_clock.cbx.xml
.............\..\elc_clock.cmp.bpm
.............\..\elc_clock.cmp.cdb
.............\..\elc_clock.cmp.ecobp
.............\..\elc_clock.cmp.hdb
.............\..\elc_clock.cmp.logdb
.............\..\elc_clock.cmp.rdb
.............\..\elc_clock.cmp.tdb
.............\..\elc_clock.cmp0.ddb
.............\..\elc_clock.cmp_bb.cdb
.............\..\elc_clock.cmp_bb.hdb
.............\..\elc_clock.cmp_bb.logdb
.............\..\elc_clock.cmp_bb.rcf
.............\..\elc_clock.dbp
.............\..\elc_clock.db_info
.............\..\elc_clock.eco.cdb
.............\..\elc_clock.fit.qmsg
.............\..\elc_clock.hier_info
.............\..\elc_clock.hif
.............\..\elc_clock.map.bpm
.............\..\elc_clock.map.cdb
.............\..\elc_clock.map.ecobp
.............\..\elc_clock.map.hdb
.............\..\elc_clock.map.logdb
.............\..\elc_clock.map.qmsg
.............\..\elc_clock.map_bb.cdb
.............\..\elc_clock.map_bb.hdb
.............\..\elc_clock.map_bb.logdb
.............\..\elc_clock.merge.qmsg
.............\..\elc_clock.pre_map.cdb
.............\..\elc_clock.pre_map.hdb
.............\..\elc_clock.psp
.............\..\elc_clock.pss
.............\..\elc_clock.rtlv.hdb
.............\..\elc_clock.rtlv_sg.cdb
.............\..\elc_clock.rtlv_sg_swap.cdb
.............\..\elc_clock.sgdiff.cdb
.............\..\elc_clock.sgdiff.hdb
.............\..\elc_clock.signalprobe.cdb
.............\..\elc_clock.sld_design_entry.sci
.............\..\elc_clock.sld_design_entry_dsc.sci
.............\..\elc_clock.sta.qmsg
.............\..\elc_clock.sta.rdb
.............\..\elc_clock.syn_hier_info
.............\..\elc_clock.tan.qmsg
.............\..\lpm_divide_e5m.tdf
.............\..\lpm_divide_htl.tdf
.............\..\sign_div_unsign_akh.tdf
.............\elc_clock.asm.rpt
.............\elc_clock.cdf
.............\elc_clock.done
.............\elc_clock.dpf
.............\elc_clock.fit.rpt
.............\elc_clock.fit.smsg
.............\elc_clock.fit.summary
.............\elc_clock.flow.rpt
.............\elc_clock.map.rpt
.............\elc_clock.map.smsg
.............\elc_clock.map.summary
.............\elc_clock.merge.rpt
.............\elc_clock.pin
.............\elc_clock.pof
.............\elc_clock.qpf
.............\elc_clock.qsf
.............\elc_clock.qws
.............\elc_clock.sof
.............\elc_clock.sta.rpt
.............\elc_clock.sta.summary
.............\elc_clock.tan.rpt
.............\elc_clock.tan.summary
.............\elc_clock.v
    

CodeBus www.codebus.net