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Description: VHDL实现50％占空比。并且是奇数分频。
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Size: 118256 |
Author: skylinnan |
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Description: 用VHDL硬件描述语言实现的良好运行的三分频电路
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Size: 1050 |
Author: 赵杰 |
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Description: VHDL实现50％占空比。并且是奇数分频。-VHDL to achieve 50 duty cycle. And is odd-numbered sub-frequency.
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Size: 117760 |
Author: skylinnan |
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Description: 用VHDL硬件描述语言实现的良好运行的三分频电路-Using VHDL hardware description language to achieve a good run of one-third frequency circuit
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Size: 1024 |
Author: 赵杰 |
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Description: flex code，compiler theory curriculum design, the C write PL / 0 compiler, a detailed documentation and code -flex code, compiler theory curriculum design, the C write PL/0 compiler, a detailed documentation and code
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Size: 39936 |
Author: yn |
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Description: 一个除3器的Verilog源码，用于视频解码器的熵解码部分。纯组合逻辑，大小和加法器差不多。-In addition to device a Verilog source code 3, the video decoder for entropy decoding part. Pure combinational logic, about the size and adder.
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Size: 106496 |
Author: 闫煜 |
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Description: 实现三分频功能，占空比为50 ，可以很好的用于解决课程设计问题！-This is used for divide the frequency,and the duty cycle is 50 .
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Size: 261120 |
Author: |
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