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[VHDL-FPGA-Verilog] double_subc

Description: Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
Platform: | Size: 146432 | Author: huangyongbing | Hits:

[VHDL-FPGA-Verilog] division_cordic

Description: verilog code for division based on cordic algorithm
Platform: | Size: 1024 | Author: meysam | Hits:

[Crack Hack] rsa

Description: 用VHDL求rsa加密系统的密钥D（辗转相除法）-Using VHDL for rsa key encryption system D（Division algorithm）
Platform: | Size: 2384896 | Author: 齐娜 | Hits:

[VHDL-FPGA-Verilog] div

Description: FPGA的IP核中除法算法的源代码，是Verilog语言的，易于初学者的学习。-FPGA IP core in the division algorithm source code, Verilog language, easy for beginners to learn.
Platform: | Size: 13312 | Author: leeyoung | Hits:

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