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Description: XC8888是XC800家族的新成员，该款芯片具有32 KB闪存，功能强大、可灵活产生PWM的捕获/比较单元(CCU6)以及用于快速数学计算的乘除单元(MDU)，使得该款芯片具有先进的电机驱动能力。 其它关键特性包括：支持LIN、高速高精度10位ADC以及坐标旋转数字计算机(CORDIC)单元。 本程序给出了ADC采样程序以及捕获比较单元CCU的两个示例，以及一个流水灯的示例程序。以上程序在工程实践中已经得到应用。开发环境为KeilC51V804。-XC800 family XC8888 is a new member, which the chip has 32 KB Flash, powerful, flexible and have a PWM capture/compare unit (CCU6), as well as mathematical calculations for fast multiplication and division unit (MDU), which makes chips with advanced electric drive capability. Other key features include: support for LIN, high-speed high-precision 10-bit ADC as well as coordinate rotation digital computer (CORDIC) module. This procedure gives the ADC sampling procedures and the capture compare unit CCU of the two examples, as well as a water sample procedures lights. Above procedures in engineering practice has been applied. Development environment for KeilC51V804.
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Size: 310272 |
Author: 余宾客 |
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Description: verilog code for division based on cordic algorithm
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Size: 1024 |
Author: meysam |
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Description: 利用cordic实现除法的matlab源码。
本人原创，标准cordic算法。-implement division by cordic.
matlab m language.
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Size: 96256 |
Author: 李林 |
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Description: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and
a configurable number of sample points in the FFT.
Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the
CFFT core to be different from the standard FFT algorithm. This variation in gain
is not important for orthogonal frequency division modulation (OFDM) and demodulation.
The gain can be corrected, to that of a conventional FFT, by applying a constant
multiplying factor.
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Size: 183296 |
Author: Nagendran |
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Description: cordic算法的matlab实现，包含除法，sin，cos，sinh，cosh等-cordic algorithm matlab realize, including the division, sin, cos, sinh, cosh, etc.
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Size: 2048 |
Author: zhangchaofan |
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Description: 本源码是基于VHDL语言环境下的基础实验源码，共分七个部分。分别是：序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, digital locks, four have signed division synchronous FIFO, DPLL design and Cordic algorithm. For beginners VHDL great reference value.
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Size: 20480 |
Author: 朱召宇 |
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