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[Other resource] 000000adada2

Description: 数据结构，二叉树和哈夫曼编码。C++ 1、 学会针对DFA转换图实现相应的高级语言源程序 ·a C++ Class Library of Cr ·简单的防火墙，可以用来学习，作为毕业课设也相当有帮 ·实现ARM 芯片的一对PWM 输出用于控制直流电机 ·Programming the Microsoft ·VC调用java的简单例子。需要注意jvm.dll ·这是介绍在VC++6。0下如何编写GPIB程序。有 ·GPS坐标转换软件：直角坐标与大地坐标转换 ·我的一个同学写的毕业论文 希望对大家来说是有用的 ·最简单的用工作线程控制有进程条的窗口,主窗口调用后 ·VC数据库编程综合应用。订单的管理 ·vhdl,用i2c控制philips的7111和7 ·基于winsock2的网络封包截获技术,源代码清楚 -data structure, binary tree and Huffman coding. C 1. Society against DFA conversion map corresponding high-level language source of a Class C of C Library r simple firewall can be used to study, as part of the graduation class is fairly established to help achieve the ARM chip of a PWM output for controlling Motor Prog ramming the Microsoft VC called java simple example. This needs attention jvm.dll is introduced in VC 6. 0 GPIB preparation procedures. Have GPS coordinates conversion software : Cartesian coordinates of the earth and converting one of my classmates wrote the dissertation hope for all of us is the most useful simple Working with a thread control of the process window, the main window after calling VC Database Programming integrated application. Vhdl orders management, i2c co
Platform: | Size: 3519 | Author: ssss3162 | Hits:

[Technology Management] 06626_DLL

Description: XILINX的DLL的使用介绍，对于时钟的应用有很大的帮助-XILINX the use of the DLL, the application for the clock will be very helpful
Platform: | Size: 1009664 | Author: fei0318 | Hits:

[Education soft system] 000000adada2

Description: 数据结构，二叉树和哈夫曼编码。C++ 1、 学会针对DFA转换图实现相应的高级语言源程序 ·a C++ Class Library of Cr ·简单的防火墙，可以用来学习，作为毕业课设也相当有帮 ·实现ARM 芯片的一对PWM 输出用于控制直流电机 ·Programming the Microsoft ·VC调用java的简单例子。需要注意jvm.dll ·这是介绍在VC++6。0下如何编写GPIB程序。有 ·GPS坐标转换软件：直角坐标与大地坐标转换 ·我的一个同学写的毕业论文 希望对大家来说是有用的 ·最简单的用工作线程控制有进程条的窗口,主窗口调用后 ·VC数据库编程综合应用。订单的管理 ·vhdl,用i2c控制philips的7111和7 ·基于winsock2的网络封包截获技术,源代码清楚 -data structure, binary tree and Huffman coding. C 1. Society against DFA conversion map corresponding high-level language source of a Class C of C Library r simple firewall can be used to study, as part of the graduation class is fairly established to help achieve the ARM chip of a PWM output for controlling Motor Prog ramming the Microsoft VC called java simple example. This needs attention jvm.dll is introduced in VC 6. 0 GPIB preparation procedures. Have GPS coordinates conversion software : Cartesian coordinates of the earth and converting one of my classmates wrote the dissertation hope for all of us is the most useful simple Working with a thread control of the process window, the main window after calling VC Database Programming integrated application. Vhdl orders management, i2c co
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[Other] DLL

Description: 关于dll的资料。非常值得看哦。欢迎下载。-Information on the dll.看哦very worthwhile. Welcome to download.
Platform: | Size: 12288 | Author: 刘峰 | Hits:

[VHDL-FPGA-Verilog] VerilogHdlPracticeAndSystemDesign

Description: 本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。-The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Chapter VII of the future design examples, not only examples of Verilog-HDL, but also attached, including VB, VC++ source code, etc., and even DLL generation methods explained in detail.
Platform: | Size: 776192 | Author: 黄虎 | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[VHDL-FPGA-Verilog] DLL

Description: 用VHDL编写的一个PLL，通过了测试，没有什么问题。-DLL
Platform: | Size: 286720 | Author: 孔令军 | Hits:

[VHDL-FPGA-Verilog] VHDL-FPGA-DLL

Description: 自动检测中英文中译英英译中百度翻译 翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop DPLL VHDL realization-自动检测中英文中译英英译中百度翻译 翻译结果（中 > 英）复制结果 A VHDL language based on all digital phase-locked loop DPLL VHDL realization
Platform: | Size: 230400 | Author: ldd | Hits:

[File Format] Dll-Files

Description: clock divider code for vhdl
Platform: | Size: 8444928 | Author: asdasd | Hits:

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