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Description: dmux realize by fpga dmux realize by fpga
Platform: |
Size: 158590 |
Author: rliivleyr |
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Description: 用VHDL编写的高速数据分流器！已经通过测试-dmux
Platform: |
Size: 555008 |
Author: 于洋 |
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Description: simple demultiplexer on 4 bits
Platform: |
Size: 3072 |
Author: vlad |
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Description: Main Features
• Quad ADC with 8-bit Resolution
– 1.25 Gsps Sampling Rate in Four-channel Mode
– 2.5 Gsps Sampling Rate in Two-channel Mode
– 5 Gsps Sampling Rate in One-channel Mode
– Built-in four-by-four Crosspoint Switch
• 2.5 GHz Differential Symmetrical Input Clock Required
• ADC Master Reset (LVDS)
• Double Data Rate Output Protocol
• LVDS Output Format
• Digital Interface (SPI) with Reset Signal
– Selectable 1:1 or 1:2 Demultiplexed Outputs
– Channel Mode Selection
– 500 mVpp or 625 mVpp Analog Input (Differential AC or DC
Coupled)
– Selectable Bandwidth (Four Available Settings)
– Gain Control (±18 )
– Offset Control (±50 mV)
– Phase Control (±14 ps Range)
– Standby Mode (Full or Partial)
– Binary or Gray Coding Selection
– Test Mode
• Power Supplies: 3.3V and 1.8V (Outputs), 1.8V (Digital)
• Power Dissipation: 4.2W Total (1:1 DMUX Mode)-Main Features
• Quad ADC with 8-bit Resolution
– 1.25 Gsps Sampling Rate in Four-channel Mode
– 2.5 Gsps Sampling Rate in Two-channel Mode
– 5 Gsps Sampling Rate in One-channel Mode
– Built-in four-by-four Crosspoint Switch
• 2.5 GHz Differential Symmetrical Input Clock Required
• ADC Master Reset (LVDS)
• Double Data Rate Output Protocol
• LVDS Output Format
• Digital Interface (SPI) with Reset Signal
– Selectable 1:1 or 1:2 Demultiplexed Outputs
– Channel Mode Selection
– 500 mVpp or 625 mVpp Analog Input (Differential AC or DC
Coupled)
– Selectable Bandwidth (Four Available Settings)
– Gain Control (±18 )
– Offset Control (±50 mV)
– Phase Control (±14 ps Range)
– Standby Mode (Full or Partial)
– Binary or Gray Coding Selection
– Test Mode
• Power Supplies: 3.3V and 1.8V (Outputs), 1.8V (Digital)
• Power Dissipation: 4.2W Total (1:1 DMUX Mode)
Platform: |
Size: 3200000 |
Author: 郭福珍 |
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