Search - ds18b20 vhdl

[Other resource] DS18B20+VHDL

Description: 用VHDL语言实现的控制DS18B20构成测温仪表的程序，包含了全部代码，可显示最高精度-with VHDL control DS18B20 constitute Thermometer procedures, contains all the code will show that the most high-precision
Platform: | Size: 818688 | Author: 刘西圣 | Hits:

[VHDL-FPGA-Verilog] DS18B20+VHDL

Description: 用VHDL语言实现的控制DS18B20构成测温仪表的程序，包含了全部代码，可显示最高精度-with VHDL control DS18B20 constitute Thermometer procedures, contains all the code will show that the most high-precision
Platform: | Size: 818176 | Author: 刘西圣 | Hits:

[Other] ds18b20

Description: 基于VHDL写的DS18B20的驱动，简单版本-based on VHDL write DS18B20 driven, simple version
Platform: | Size: 299008 | Author: zhaoyang | Hits:

[VHDL-FPGA-Verilog] DS18B20_VHDL

Description: FPGA DS18B20 测试温度 VHDL源码 -FPGA DS18B20 test temperature VHDL source code
Platform: | Size: 152576 | Author: 张焱 | Hits:

[VHDL-FPGA-Verilog] ds18b20vddl

Description: 传感器ds18b20 与 FPGA 通信实现方式-Sensor DS18B20 way communication with the FPGA
Platform: | Size: 1024 | Author: 石平政 | Hits:

[VHDL-FPGA-Verilog] temperature

Description: 基于VHDL控制的DS18B20温度测量程序，精确到小数点后两位，在实验板上通过；-VHDL-based control procedures DS18B20 temperature measurement, accurate to two decimal places, the board adopted in the experiment
Platform: | Size: 2048 | Author: liao | Hits:

[VHDL-FPGA-Verilog] DS18B20FPGA

Description: VHDL设计的ds18b20的测温程序，欢迎测试请不要直接复制，可能不好显示。-VHDL design of the measurement procedures DS18B20 welcome Please do not directly copy the test may not show.
Platform: | Size: 7168 | Author: aaaa | Hits:

[VHDL-FPGA-Verilog] DS18B20

Description: 用VHDL写的DS18B20温度采集程序，QuartusII的完整工程，控制灵活，易扩展-Using VHDL written DS18B20 temperature acquisition procedures, QuartusII complete projects, flexible control and easy expansion
Platform: | Size: 100352 | Author: wanyou | Hits:

[SCM] DS18B20

Description: 基于单片机的DS18B20温度采集系统实时温度采集具有报警功能-DS18B20 temperature based on single-chip real-time acquisition system with alarm function of temperature acquisition
Platform: | Size: 151552 | Author: zhouhongxi | Hits:

[VHDL-FPGA-Verilog] ds18b20

Description: ds18b20的介绍及时序，以及对ds18b20进行温度读写的vhdl程序，在quartus环境下进行编译仿真-Introduction ds18b20 and timing, as well as read and write ds18b20 temperature vhdl procedure quartus compiled simulation environment
Platform: | Size: 14336 | Author: dreamy | Hits:

[VHDL-FPGA-Verilog] DS18b20

Description: 这是一个工业用的普通温度传感器DS18b20的VHDL文件，直接可用，可为FPGA的其他逻辑模块或者Nios提供接口，其输出为18b20的11位温度暂存器的值。-This is a common logic module for DS18b20 which can provides parallel outputs for Nios II or other internal units of FPGA.
Platform: | Size: 2048 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] ds18b20

Description: 这是基于NIOS II的 DS18B20 的源码，绝对可用本人已经调试成功，希望对大家有-It s a DS18B20 code for nios ii.
Platform: | Size: 1673216 | Author: tom | Hits:

[Other] DS18B20

Description: 8位单片机与DS18B20并行双向通信。 Quartus II 8.1项目工程文件. 主源程序文件为DS18B20.v,里面有详细注解。例子： DS18B20 数据地址 0xf000（ROM=0） DS18B20 ROM指令地址 0xf001（ROM=1）外部电源供电且只有一DS18B20的读取法：发送CC到0xf001, 等待busy=0说明器件已准备好, 读0xf001的Bit1=1说明存在器件,Bit0=1为控制忙(可以省略此步）发送44到0xf000, 等待busy=0，发送CC到0xf001，等待busy=0，发送BE到0xf000，等待busy=0，空读一次，等待busy=0，然后读到的就是DS18B20内部数据了.读一次必须等待busy=0，否则控制器将拒绝所有操作。搜索ROM：发送F0或EC到0xf001, 等待busy=0说明器件已准备好, 读0xf001的Bit1=1说明存在器件,Bit0=1为控制忙(可以省略此步）空读0xf000，（第1次）等待busy=0，读0xf000，Bit0是DS18B20发送位的信息，Bit1为DS18B20发送位的补码信息等待busy=0，写0xf000，内容为路径。等待busy=0，。。。。。。空读0xf000，（第64次）等待busy=0，读0xf000，Bit0是DS18B20发送位的信息，Bit1为DS18B20发送位的补码信息等待busy=0，写0xf000，内容为路径。等待busy=0，结束 -8-bit microcontroller with DS18B20 parallel two-way communication. Quartus II 8.1 Project documents. Primary source documents DS18B20.v, which detailed notes. Example: DS18B20 Data Address 0xf000 (ROM = 0) DS18B20 ROM instruction address 0xf001 (ROM = 1) An external power supply and only a DS18B20 read method: Send CC to 0xf001, Wait for busy = 0 shows the device is ready, Read 0xf001 the existence of Bit1 = 1 shows the device, Bit0 = 1 for the control of busy (you can omit this step) Send 44 to 0xf000, Wait for busy = 0, Send CC to 0xf001, Wait for busy = 0, Send BE to 0xf000, Wait for busy = 0, Blank reading time, Wait for busy = 0, Then read is DS18B20 internal data. Read one must wait for the busy = 0, otherwise the controller will reject all operations. Search ROM: Send F0 or EC to 0xf001, Wait for busy = 0 shows the device is ready, Read 0xf001 the existence of Bit1 = 1 shows the device, Bit0 = 1 for the control of busy (you can omi
Platform: | Size: 338944 | Author: yuantielei | Hits:

[VHDL-FPGA-Verilog] ds18b20-vhdl

Description: vhdl写的ds18b20程序，相互交流-vhdl written ds18b20 procedures, mutual exchange
Platform: | Size: 1024 | Author: yudezhao | Hits:

[Other] ds18b20

Description: 改程序实现了对dalas的1-wire器件温度传感器ds18b20（也可以是ds1825）的驱动，并将温度值显示在液晶屏幕1602上-This program is dedicated to driving the 1-wire device ds18b20(ds1825),which reads the temperature and displays it on the LHD1602
Platform: | Size: 4068352 | Author: mn | Hits:

[Embeded-SCM Develop] DS18B20_VHDL

Description: DS18B20 VHDL 配置程序，fpga 验证，可以实现配置-DS18B20 VHDL configuration program, fpga verification, configuration can be achieved
Platform: | Size: 570368 | Author: 李宗州 | Hits:

[VHDL-FPGA-Verilog] ds18b20

Description: 单路DS18B20的verilog HDL 代码，精度为1℃无须转换数据，直接输出结果。占用300个LE资源。-Single DS18B20 the verilog HDL code, and an accuracy of 1 ℃ without converting the data, direct output. Occupy 300 LE resources.
Platform: | Size: 443392 | Author: chenwl | Hits:

[VHDL-FPGA-Verilog] DS18B20

Description: 基于vhdl的温度控制器（选用ds18b20）-The temperature controller based on vhdl (optional ds18b20)
Platform: | Size: 898048 | Author: 何思 | Hits:

[VHDL-FPGA-Verilog] FPGA-and-DS18B20

Description: FPGA与测温芯片DS18B20的通信实现，用verilog语言编写。有实际验证过的工程，有实验报告，有DS18B20的资料，适合快速了解。-FPGA chip with the DS18B20 temperature achieved with verilog language. Verified with the actual project, there are experimental reports, the DS18B20 data for quick understanding.
Platform: | Size: 1205248 | Author: r | Hits:

[VHDL-FPGA-Verilog] DS18B20-VHDL-program

Description: DS18B20的VHDL程序,很好，简短易懂。-DS18B20 VHDL program, well, brief and easy to understand.
Platform: | Size: 3072 | Author: 罗庆群 | Hits:

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[Other resource] DS18B20+VHDL

[VHDL-FPGA-Verilog] DS18B20+VHDL

[Other] ds18b20

[VHDL-FPGA-Verilog] DS18B20_VHDL

[VHDL-FPGA-Verilog] ds18b20vddl

[VHDL-FPGA-Verilog] temperature

[VHDL-FPGA-Verilog] DS18B20FPGA

[VHDL-FPGA-Verilog] DS18B20

[SCM] DS18B20

[VHDL-FPGA-Verilog] ds18b20

[VHDL-FPGA-Verilog] DS18b20

[VHDL-FPGA-Verilog] ds18b20

[Other] DS18B20

[VHDL-FPGA-Verilog] ds18b20-vhdl

[Other] ds18b20

[Embeded-SCM Develop] DS18B20_VHDL

[VHDL-FPGA-Verilog] ds18b20

[VHDL-FPGA-Verilog] DS18B20

[VHDL-FPGA-Verilog] FPGA-and-DS18B20

[VHDL-FPGA-Verilog] DS18B20-VHDL-program

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