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[VHDL-FPGA-Verilogfftmatlab

Description: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 7168 | Author: zqh | Hits:

[VHDL-FPGA-VerilogFSK_work

Description: 自己做的基于MATLAB DSP BUILDER的FSK,里面的内容都在,整个工程-MY FSK,have cost much time。please use it carefully。
Platform: | Size: 713728 | Author: 朱铭进 | Hits:

[DSP programdspddc_R12p1

Description: 基于DSPbuilder搭建的DDC,里面包括CIC滤波器,FIR低通滤波器,HB半带滤波器,NCO等,实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
Platform: | Size: 17408 | Author: 郑程 | Hits:

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