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Description: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
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Size: 270336 |
Author: 黄鹤 |
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Description: 這是一個DWT的Verilog code,它的主要功用是PC與FPGA之間的DWT程序的溝通與傳輸-This is a DWT of the Verilog code, its main function is between the PC and FPGA communication DWT procedures and transmission
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Size: 1467392 |
Author: chiahao |
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Description: 本文提出了一种基于提升算法的高效JPEG2000二维离散小波变换(2D—DWT)~ 结构，将边界延拓内嵌于离散小波变换过程中，减少了所需的内存空间和功耗。采用W 扫描输入方式和行列并行处理结构，加快了变换速度，大大提高了小波变换的效率。整个二维离散小波变换结构已经通过FPGA硬件仿真验证。-This paper presents a highly efficient algorithm based on lifting JPEG2000 two-dimensional discrete wavelet transform (2D-DWT) ~ structure, the boundary extension will be embedded in the process of discrete wavelet transform to reduce the required memory space and power consumption. W scanning input methods used and the ranks of parallel processing structure, and accelerated the pace of change has greatly enhanced the efficiency of wavelet transform. The whole structure of two-dimensional discrete wavelet transform has been adopted FPGA hardware simulation.
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Size: 182272 |
Author: H Simon |
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Description: 个人收集的FPGA图像压缩算法包，包括内容主要为图像压缩算法DWT 离散小波变换
DCT 离散余弦变换
SHIHT 多级树集合划分
EBCOT优化截取的嵌入式块编码等-Personal collection of image compression algorithm for FPGA package, including the contents of the main image compression algorithm for the discrete wavelet transform DWT discrete cosine transform DCT multi-level tree SHIHT set partitioning optimization interception EBCOT Embedded Block Coding, etc.
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Size: 6079488 |
Author: sdf |
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Description: Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
-Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
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Size: 1474560 |
Author: jeason |
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Description: 图像压缩是图像处理中的一个重要课题，在减少图像尺寸以实时传输和存储方面起着非常重要的作用。许多标准推荐使用DWT进行图像压缩。DWT的计算复杂度对基于DWT的图像压缩算法的实时使用提出了重大挑战。在本文中，我们提出了一种改进的提升方案来计算近似和详细的DWT系数。修正的方程使用右移运算符和6位乘法器。计算中的层级减少到一个，从而最小化延迟和增加吞吐量。ViTEX-5 FPGA上实现的设计工作在180 MHz，功耗小于1W的功率。该设计占用了FPGA上不到1的LUT资源。所开发的体系结构适合于FPGA平台上的实时图像处理。(Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The computational complexity of DWT imposes a major challenge for the real-time use of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for computing the approximation and detailed coefficients of DWT. The modified equations use, right shift operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The architecture developed is suitable for real-time image processing on FPGA platform.)
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Size: 1473536 |
Author: asde198250 |
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