Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis
2. fpga implemention of a median filter
3. fpga implementation of digital filters
4.hardware acceleration of edge detection algorithm on fpgas
5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages
6. implementing 2D median filter in fpgas
7.视频图像处理与分析的网络资源 Platform: |
Size: 1969152 |
Author:carol |
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Description: Abstract—This paper proposes a new technique for face detection
and lip feature extraction. A real-time field-programmable
gate array (FPGA) implementation of the two proposed techniques
is also presented. Face detection is based on a naive Bayes classifier
that classifies an edge-extracted representation of an image. Using
edge representation significantly reduces the model’s size to only
5184 B, which is 2417 times smaller than a comparable statistical
modeling technique, while achieving an 86.6 correct detection
rate under various lighting conditions. Lip feature extraction uses
the contrast around the lip contour to extract the height and width
of the mouth, metrics that are useful for speech filtering. The
proposed FPGA system occupies only 15 050 logic cells, or about
six times less than a current comparable FPGA face detection
system.-Abstract—This paper proposes a new technique for face detection
and lip feature extraction. A real-time field-programmable
gate array (FPGA) implementation of the two proposed techniques
is also presented. Face detection is based on a naive Bayes classifier
that classifies an edge-extracted representation of an image. Using
edge representation significantly reduces the model’s size to only
5184 B, which is 2417 times smaller than a comparable statistical
modeling technique, while achieving an 86.6 correct detection
rate under various lighting conditions. Lip feature extraction uses
the contrast around the lip contour to extract the height and width
of the mouth, metrics that are useful for speech filtering. The
proposed FPGA system occupies only 15 050 logic cells, or about
six times less than a current comparable FPGA face detection
system. Platform: |
Size: 28409856 |
Author:ramanaidu |
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Description: 采用VHDL语言编写的边缘检测源代码，在xilinx公司的spatan-3an的仿真版上验证无误，供初学者学习-Edge detection using VHDL language source code, verification, simulation version of the company spatan-3an xilinx for beginners to learn Platform: |
Size: 12288 |
Author:纪坤 |
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Search - edge detection using vhdl