Search - edge detection using vhdl

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[Fractal program] videoprocessor DL : 0: 边沿检测，用vhdl实现sobel算子。-Edge detection, using VHDL realize sobel operator.
Date : 2025-07-11 Size : 7.72mb User : 大洪
[Software Engineering] Digital_Filter_implementation_by_FPGA DL : 0: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on fpgas 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in fpgas 7.视频图像处理与分析的网络资源
Date : 2025-07-11 Size : 1.88mb User : carol
[VHDL-FPGA-Verilog] TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA DL : 0: Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.-Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model’s size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6 correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system.
Date : 2025-07-11 Size : 27.09mb User : ramanaidu
[Mathimatics-Numerical algorithms] edge_detection_morphological DL : 0: edge detection using morphological way..sober and dilation implementation
Date : 2025-07-11 Size : 36kb User : sachin
[Mathimatics-Numerical algorithms] edgedetect DL : 0: image edge detection using vhdl
Date : 2025-07-11 Size : 624kb User : sachin
[Mathimatics-Numerical algorithms] edgewen DL : 0: edge detection using vhdl
Date : 2025-07-11 Size : 375kb User : sachin
[VHDL-FPGA-Verilog] vhdl-program DL : 0: sobel edge detection using vhdl
Date : 2025-07-11 Size : 106kb User : hamed
[VHDL-FPGA-Verilog] edge_detect DL : 0: 采用VHDL语言编写的边缘检测源代码，在xilinx公司的spatan-3an的仿真版上验证无误，供初学者学习-Edge detection using VHDL language source code, verification, simulation version of the company spatan-3an xilinx for beginners to learn
Date : 2025-07-11 Size : 12kb User : 纪坤