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[Otherencode_bit

Description: 关于turbo码编码的仿真程序,简单实用,是初学者的理想程序-On the turbo coding of the simulation program, simple and practical, is the ideal program for beginners
Platform: | Size: 3072 | Author: 仲楷 | Hits:

[VHDL-FPGA-VerilogSRAM_controller_of_FPGA

Description: 视频处理源码,使用pdf格式输出,用的时候自解压,然后拷贝黏贴就行了。-`timescale 1ns/1ns module asyn_fifo(clk_wr,wr_en,clk_rd,rd_en,rst,din,full,empty,dout) input clk_wr,wr_en,clk_rd,rd_en,rst input[7:0] din output full,empty output[7:0] dout reg full_temp,empty_temp,full_temp1,empty_temp1 wire full,empty wire[7:0] dout reg[9:0] cnt_wr,cnt_rd,encode_cnt_wr,encode_cnt_rd wire[9:0] gray_cnt_wr,gray_cnt_rd integer i reg[9:0] encode_a,encode_b,tempa,tempb
Platform: | Size: 59392 | Author: YZX | Hits:

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