Search - encoder vhdl

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[Embeded-SCM Develop] 卷积码、CRC

Description: 卷积码的C源程序，包括编码器和译码器。还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6144 | Author: 潘华林 | Hits:

[VHDL-FPGA-Verilog] encoder

Description: VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。-VHDL realization of cyclic code encoding, designed three modules. switch is a switch, shifter is the shift register, encoder is the main.
Platform: | Size: 2048 | Author: 王三一 | Hits:

[VHDL-FPGA-Verilog] crc_verilog

Description: 循环码编码器verilog实现，里面包含有源程序和仿真图。-Cyclic code encoder Verilog realization, which contains the source code and simulation of Fig.
Platform: | Size: 15360 | Author: 萍果 | Hits:

[Compress-Decompress algrithms] rs_encoder

Description: 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。-A very good RS encoder for DVB Channel Coding using VHDL language, in the FPGA-validated.
Platform: | Size: 3072 | Author: 杨宇 | Hits:

[SCM] CPLD

Description: 控制三相步进电机及光电编码器的采集,当电机停止时,保证三相里面只有一相相通,防止停止时电流过大.-Control three-phase stepper motor and optical encoder collection, when the motor stops to ensure that only one phase of three-phase inside the heart, and to prevent too much current is stopped.
Platform: | Size: 580608 | Author: suifeg | Hits:

[Software Engineering] AB_PHASE_PWM_SOPC

Description: AB相编码器解码接口、PWM输出SOPC议案及其在运动控制卡和伺服驱动器中的应用-AB phase encoder decoder interface, PWM output SOPC motion and in motion control card and servo drive applications
Platform: | Size: 402432 | Author: 张贺 | Hits:

[Communication-Mobile] RSencoder

Description: 关于rs码编码器的相关程序，利用硬件语言实现-Rs encoder code on the relevant procedures, take advantage of the hardware language
Platform: | Size: 5120 | Author: 庄镒鹏 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Platform: | Size: 256000 | Author: mediative | Hits:

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

Description: 旋转编码器的decoder，具有消颤音功能-Rotary encoder decoder, with a vibrato function elimination
Platform: | Size: 280576 | Author: 于水 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 最高优先级编码器和直流电机控制器,供初学者学习使用，方便快捷，有很强的参考价值-The highest priority encoder and DC motor controller, for beginners learning to use, convenient and has a strong reference value
Platform: | Size: 3072 | Author: 张楚荀 | Hits:

[VHDL-FPGA-Verilog] crcm

Description: crc 校验，vhdl源码，经仿真能正常运行，供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Platform: | Size: 1024 | Author: fangliang | Hits:

[VHDL-FPGA-Verilog] CRC16bits

Description: 16bit crc encoder ande demo
Platform: | Size: 167936 | Author: chen | Hits:

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

Description: Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Rotary Encoder InterfaceDemonstrates how to use the rotary encoder portion of the rotary pushbutton switch.
Platform: | Size: 279552 | Author: weihua yuan | Hits:

[VHDL-FPGA-Verilog] oc_mkjpeg

Description: Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Platform: | Size: 3267584 | Author: Andy | Hits:

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[SCM] VHDL范例

[Embeded-SCM Develop] 卷积码、CRC

[VHDL-FPGA-Verilog] encoder

[VHDL-FPGA-Verilog] crc_verilog

[Compress-Decompress algrithms] rs_encoder

[SCM] CPLD

[Software Engineering] AB_PHASE_PWM_SOPC

[Communication-Mobile] RSencoder

[VHDL-FPGA-Verilog] viterbi

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] crcm

[VHDL-FPGA-Verilog] CRC16bits

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

[VHDL-FPGA-Verilog] oc_mkjpeg

[VHDL-FPGA-Verilog] A-law_enc

[Windows Develop] xapp339

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] vhdl-JPEG-enc

[Compress-Decompress algrithms] jpegencode_latest.tar

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