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Description: 使用Usb cy7c68013与DSP通信，现在已经能够很正确的传递（上传数据）了。
USB资源：
使用了Ep２，Ep６
Ep2, out auto
Ep6, in auto
FlagA－－－ PF3
FlagB－－－ PF6
FlagC－－－ PF1
需要 EP２ EMPTY
EP6 FULL信号
因此
FlagA－－－ PF3 －－－ EP2空 －－－ ８ h
FlagB－－－ PF6 －－－ EP6满 －－－ e h
FlagC－－－ PF1
PINFLAGSAB＝0xE8
极性设置：
PKTEND，EPEF，EPFF high
其他的低
因此 FIFOPINPOLAR = 0x23
包结束信号接在DSP 的 PF７ 上面。
以上结束06.11.28
Platform: |
Size: 28436 |
Author: 张衡 |
Hits:
Description: The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed
to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6
as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up
the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are
ready for data operations
Platform: |
Size: 46792 |
Author: 崔卫 |
Hits:
Description: usb 端点测试程序 块传输
从EP6输入512字到EP2传出。
Platform: |
Size: 43809 |
Author: 张那 |
Hits:
Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码
Platform: |
Size: 1012462 |
Author: 李华 |
Hits:
Description: C语言编写的简单计算程序的语法分析器，可以识别一定的计算功能-C language prepared by the simple calculation procedure syntax analyzer can identify certain computing capabilities
Platform: |
Size: 1024 |
Author: 刘思远 |
Hits:
Description: Cyclone II EP2C5实验开发板原理图PDF文件-Cyclone II development board EP2C5 experimental diagram PDF files
Platform: |
Size: 444416 |
Author: 高 |
Hits:
Description: 使用Usb cy7c68013与DSP通信，现在已经能够很正确的传递（上传数据）了。
USB资源：
使用了Ep２，Ep６
Ep2, out auto
Ep6, in auto
FlagA－－－ PF3
FlagB－－－ PF6
FlagC－－－ PF1
需要 EP２ EMPTY
EP6 FULL信号
因此
FlagA－－－ PF3 －－－ EP2空 －－－ ８ h
FlagB－－－ PF6 －－－ EP6满 －－－ e h
FlagC－－－ PF1
PINFLAGSAB＝0xE8
极性设置：
PKTEND，EPEF，EPFF high
其他的低
因此 FIFOPINPOLAR = 0x23
包结束信号接在DSP 的 PF７ 上面。
以上结束06.11.28
-Usb cy7c68013 with the use of DSP Communications, and now already in place to correct the transmission (upload data) a. USB resources: the use of Ep2, Ep6 Ep2, out auto Ep6, in auto FlagA--- PF3 FlagB--- PF6 FlagC--- PF1 need EP2 EMPTY EP6 FULL signal therefore FlagA--- PF3--- EP2 empty--- 8 h FlagB--- PF6--- EP6 full--- e h FlagC--- PF1 PINFLAGSAB = 0xE8 polarity settings: PKTEND, EPEF, EPFF high the other low-FIFOPINPOLAR = 0x23 packet, therefore the end of the signal received at the DSP
Platform: |
Size: 28672 |
Author: 张衡 |
Hits:
Description: The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed
to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6
as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up
the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are
ready for data operations-The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speedto 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets upthe FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they areready for data operations
Platform: |
Size: 107520 |
Author: 崔卫 |
Hits:
Description: usb 端点测试程序 块传输
从EP6输入512字到EP2传出。-usb endpoint testing procedures block transfer input 512 from EP6 spread the word to EP2.
Platform: |
Size: 44032 |
Author: 张那 |
Hits:
Description:
Platform: |
Size: 367616 |
Author: sun huaiming |
Hits:
Description: cpld ep240硬件开发图纸文档,为CPLD开发提供平台-hardware development cpld ep240 drawings documents, provide a platform for CPLD Development
Platform: |
Size: 60416 |
Author: |
Hits:
Description: 使用68013的测试程序，包含68013固件程序（采用slave FIFO bulk同步读写，EP2 OUT，EP6 IN），驱动，PC端测试用程序。CPLD的VHDL代码-Test procedures for the use of 68,013, including 68,013 firmware (using the synchronous slave FIFO bulk read and write, EP2 OUT, EP6 IN), driver, PC-side test procedures. VHDL code of CPLD
Platform: |
Size: 4731904 |
Author: 李华 |
Hits:
Description: 很好的资料和大家分享 飓风板的原理图-Good to share information and hurricane board schematics
Platform: |
Size: 119808 |
Author: 王之希 |
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Description: usb数据采集-附件程序-cypress68013-完成从ad进行数据的采样-usb data acquisition- Annex procedures-cypress68013-completed data from the ad sample
Platform: |
Size: 89088 |
Author: 郁闷 |
Hits:
Description: Altera FPGA Cyclone II EP2C5 最小系统 开发板-the minimum system of Altera FPGA EP2C5 and or EP2C8
Platform: |
Size: 588800 |
Author: 长官林 |
Hits:
Description: ep2c8 protel dxp 原理图和PCB版图,希望对各为有用.-ep2c8 protel dxp schematic and PCB layout, in the hope that the most useful.
Platform: |
Size: 1657856 |
Author: 吴勇 |
Hits:
Description: 通过使用matlab软件实现fir滤波器-fir filter
Platform: |
Size: 1024 |
Author: Fung |
Hits:
Description: It makes program EP2.CPP in C/C++ that, given an image in levels of gray m? .tga with letters H, V, W, X (arial boldface, different rotations and scales), creates binarizada image b? .bmp e, after that, creates colorful image c? .jpg painting each letter of a color. For example, executing the command below, we must get the images b1.bmp and c1.jpg.
Platform: |
Size: 827392 |
Author: Rodrigo |
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Description: altera
FPGA EP2C5Q208/EP2C8Q208原理图和PCB及测试程序-altera
FPGA EP2C5Q208/EP2C8Q208
Platform: |
Size: 640000 |
Author: zch |
Hits:
Description: The Source launcher for the game Grand Chase Season V EP2.
Platform: |
Size: 72969324 |
Author: Zore93 |
Hits: