Description: 眨眼检测，先用haar特征框定人脸，然后用camshift跟踪人脸，根据几何特征得到人眼的大概位置，然后根据直方图的变化检测眨眼-Blink detection, the first feature with the haar framed face, and then use camshift tracking human face, according to the geometric features are the approximate location of the human eye, and then change detection histogram blink of an eye Platform: |
Size: 5120 |
Author:阿强 |
Hits:
Description: Abstract—This paper proposes a new technique for face detection
and lip feature extraction. A real-time field-programmable
gate array (FPGA) implementation of the two proposed techniques
is also presented. Face detection is based on a naive Bayes classifier
that classifies an edge-extracted representation of an image. Using
edge representation significantly reduces the model’s size to only
5184 B, which is 2417 times smaller than a comparable statistical
modeling technique, while achieving an 86.6 correct detection
rate under various lighting conditions. Lip feature extraction uses
the contrast around the lip contour to extract the height and width
of the mouth, metrics that are useful for speech filtering. The
proposed FPGA system occupies only 15 050 logic cells, or about
six times less than a current comparable FPGA face detection
system.-Abstract—This paper proposes a new technique for face detection
and lip feature extraction. A real-time field-programmable
gate array (FPGA) implementation of the two proposed techniques
is also presented. Face detection is based on a naive Bayes classifier
that classifies an edge-extracted representation of an image. Using
edge representation significantly reduces the model’s size to only
5184 B, which is 2417 times smaller than a comparable statistical
modeling technique, while achieving an 86.6 correct detection
rate under various lighting conditions. Lip feature extraction uses
the contrast around the lip contour to extract the height and width
of the mouth, metrics that are useful for speech filtering. The
proposed FPGA system occupies only 15 050 logic cells, or about
six times less than a current comparable FPGA face detection
system. Platform: |
Size: 28409856 |
Author:ramanaidu |
Hits:
Description: 基于fpga的人脸识别，包括硬件平台的搭建的详细过程，人脸识别算法的详细程序代码。-Fpga-based face recognition, including the hardware platform to build a detailed process of face recognition algorithm detailed code. Platform: |
Size: 432128 |
Author:tiger |
Hits:
Description: 基于adoost的fpga人脸检测程序，代码采用了verilog编写，用的是xilinx的virtex5芯片-face detection based on adboost. verilog is used，and virtex5 it isimplementated on virtex5. Platform: |
Size: 8312832 |
Author:张驠 |
Hits:
Description: this is fpga BASED HAAR like feature for face detection
it s include algorithms and explanations of haar features
-this is fpga BASED HAAR like feature for face detection
it s include algorithms and explanations of haar features
Platform: |
Size: 640000 |
Author:saif king |
Hits:
Description: THIS IS A PROCEDURE FOR DESIGNING FACE DETECTION AND IMPLEMENTING ON FPGA BY USING GAUSSIAN FILTER DWT AND OTHER IMPORTANT BLOCKS Platform: |
Size: 835584 |
Author:raj |
Hits:
Description: 人脸检测与跟踪是一个重要而活跃的研究领域，它在视频监控、生物特征识别、视频编码等领域有着广泛的应用前景。该项目的目标是在FPGA板上实现实时系统来检测和跟踪人脸。人脸检测算法包括肤色分割和图像滤波。通过计算被检测区域的质心来确定人脸的位置。该算法的软件版本独立实现，并在matlab的静止图像上进行测试。虽然从MATLAB到Verilog的转换没有预期的那样顺利，实验结果证明了实时系统的准确性和有效性，甚至在不同的光线、面部姿态和肤色的条件下也是如此。所有硬件实现的计算都是以最小的计算量实时完成的，因此适合于功率受限的应用。(Face detection and tracking is an important and active research field, and it has a wide range of applications in video surveillance, biometrics, video coding and other fields. The goal of the project is to implement real-time systems on the FPGA board to detect and track faces. Face detection algorithms include skin segmentation and image filtering. The location of the human face is determined by calculating the centroid of the detected region. The software version of the algorithm is implemented independently and tested on MATLAB still images. Although the conversion from MATLAB to Verilog is not as smooth as expected, the experimental results demonstrate the accuracy and effectiveness of real-time systems, even in different light, facial gestures and color conditions. All hardware implementations are performed in real-time with minimal computational complexity and are therefore suitable for power constrained applications.) Platform: |
Size: 63488 |
Author:合发
|
Hits:
Search - face detection FPGA