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[VHDL-FPGA-Verilog] mul_booth

Description: 基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source
Platform: | Size: 2048 | Author: df | Hits:

[VHDL-FPGA-Verilog] 8bit_mult

Description: 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
Platform: | Size: 47104 | Author: 孙世玮 | Hits:

[VHDL-FPGA-Verilog] 72

Description: 7:2乘法器 ，应用verilog语言 ，快速高效，使用了华莱士树-Dragging on time-multiplier, application verilog language, fast and efficient, the use of the Wallace tree
Platform: | Size: 8192 | Author: gaod | Hits:

[DSP program] book3e

Description: 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
Platform: | Size: 1870848 | Author: 刘许军 | Hits:

[VHDL-FPGA-Verilog] fast_radix10

Description: fpga implementation of fast radix 10 multiplier using verilog code
Platform: | Size: 3633152 | Author: karthick | Hits:

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