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Description: 详细介绍nios DMA范例,很有帮助的.-Nios DMA detailed examples, very helpful.
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Size: 6144 |
Author: 朱蒙蒙 |
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Description: 关于用c2h实现fft算法的源代码和说明书 altera-On C2H achieve fft algorithm using the source code and a detailed description of altera
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Size: 723968 |
Author: 梁山皮 |
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Description: 基于FPGA的fft实现
摘要:本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核,代替传统DSP芯片或高性能单片机,实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core (Nios) soft-core processor, chip or replace the traditional high-performance single-chip DSP to realize the audio signals based on FFT analysis .
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Size: 32768 |
Author: xiang |
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Description: 在nios的集成开发环境中,实现了1024点的fft运算,并可以硬件加速-In nios integrated development environment, the realization of a 1024 point fft computation, and can be hardware-accelerated
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Size: 13312 |
Author: 黄易飞 |
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Description: 1024点FFT运算的软件实现方法,可移植NIOS和ARM,有详细说明-1024-point FFT method of computing software, portable NIOS and ARM, is described in detail
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Size: 165888 |
Author: shaw |
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Description: 2048 fft 定点C程序,可以在nios CPU中使用。-2048 fft fixed-point C program, you can use the nios CPU.
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Size: 27648 |
Author: panchao |
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Description: 用NIOS2核建的FFT工程,能够对输入的数据进行FFT或IFFT变换。-FFT with NIOS2 nuclear construction projects, to input data on FFT or IFFT transform.
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Size: 45225984 |
Author: 米多 |
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Description: 适用于NIOS II的1024点FFT C算法- 1024-point FFT C algorithm for NIOS II
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Size: 2048 |
Author: ogrex |
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Description: 优秀硕士论文,课题采用现场可编程门阵列((FPGA),设计实现了一种超高速FFT处理器。目前,使用FPGA实现FFT多采用基2和基4结构,随着FPGA规模的不断扩大,使采用更高基数实现FFT变换成为可能。本课题就是采用Alter的Stratix II芯片完成了基16-FFT处理器的设计。在设计实现过程中,以基2-FFT搭建基16-FFT的运算核,合理安排时序,解决了碟形运算、数据传输和存储操作协调一致的问题。由于采用流水线工作方式,使整个系统的数据交换和处理速度得以很大提高。本设计实现了4096点和256点的变换,两个内部运算时钟都可以达到1 OOMHz以上,其中256点变换的数据吞吐率高达1.36GHz
-a design of ultra high speed FFT processor based onFPGA is developed in this paper. At present we always use radix-2 and radix-4 tocarry out FFT. When the scale of FPGA is panding,it s possible to implement higher radix FFT. This topic uses Stratix II of Altera company to carry out a
processor of radix一16 FFT.In this design, radix-16 FFT is carried out by radix-2FFT, The design uses rational time sequence arrangement to make butterflycomputing,data transformation and memory coincide.In order to avoid the
bottleneck,pipeline pattern is used,this method acceletates the operating.Thescheme realizes the 4096-points and 256-points FFT, their operation clocks canboth reach above 100MHz. Among them ,the throughput of 256-points FFT is up to1.36GHz.
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Size: 3759104 |
Author: 陈子牙 |
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Description: VHDL NIOS-II FFT 频谱分析仪-this is a anloay by FPGA
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Size: 699392 |
Author: 彭倜 |
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Description: FFT的c语言实现,已经成功在FPGA的NIOS II软核里实现-FFT of c language has been successfully implemented in the FPGA NIOS II soft-core
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Size: 1024 |
Author: 梦一般的虚幻 |
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Description: 时域基2快速傅里叶变换算法,在nios ii处理器中实现的一种 fft功能算法,可用于频谱分析。-Time domain radix-2 FFT algorithm, implemented in the nios ii processor features an fft algorithm can be used for spectral analysis.
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Size: 2048 |
Author: 张光 |
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Description: 基于NIOS II的fft程序,使用C语言编写实现快速傅里叶变换-FFT based on NIOS II, using C language to realize the fast Fourier transform
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Size: 1024 |
Author: 康乐 |
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Description: 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核的基于FFT的音频信号分析仪-Based on Altera Cyclone II series FPGA embedded high-performance embedded IP core (Nios) soft core processor FFT-based audio signal analyzer
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Size: 155648 |
Author: 张文 |
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Description: 应用SPOC技术在FPGA平台上开发双核NIOS II软核,来并行处理FFT浮点运算,从而加快数字信号的处理效率。-SPOC technology application development platform in the FPGA NIOS II soft-core dual-core, floating point FFT in parallel processing to speed up the processing efficiency of the digital signal.
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Size: 3072 |
Author: 杨涛 |
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Description: 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核,实现了基于FFT的音频信号分析-Altera Cyclone II FPGA family based embedded high-performance embedded IP core (Nios) soft core processor to achieve a FFT-based audio signal analysis
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Size: 2048 |
Author: 季云 |
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Description: 基于kaiser窗的双谱线插值FFT谐波分析,实现用SDRAM运行nios,同时用SRAM保存摄像头数据,有较好的参考价值。- Dual-line interpolation FFT harmonic analysis kaiser windows, Implemented with SDRAM run nios, while saving camera data SRAM, There are good reference value.
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Size: 6144 |
Author: 马小雪 |
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Description: 实现用SDRAM运行nios,同时用SRAM保存摄像头数据,LZ复杂度反映的是一个时间序列中,基于kaiser窗的双谱线插值FFT谐波分析。- Implemented with SDRAM run nios, while saving camera data SRAM, LZ complexity is reflected in a time sequence, Dual-line interpolation FFT harmonic analysis kaiser windows.
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Size: 6144 |
Author: kingbenmanniu |
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Description: ofdm system simulation including 16qam modulation fft windowing modules plus cp, Implemented with SDRAM run nios, while saving camera data SRAM, Stepwise linear regression.
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Size: 5120 |
Author: meigengping
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Description: Embedded SoPC Design with Nios II Processor and Verilog Examples
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Size: 657408 |
Author: davido
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