Description: FFT处理器的FPGA设计,详细论证设计方案,希望对大家有所帮助。-FFT processor, FPGA design, detailed design verification program, and they hope to be helpful to everyone. Platform: |
Size: 122880 |
Author: |
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Description: Verilog教程,讲述Verilog在cpld/fpga中从设计到仿真全过程。-Verilog tutorial, Verilog described in cpld/fpga simulation from the design to the entire process. Platform: |
Size: 2479104 |
Author:pangyugang |
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Description: 基4-FFT蝶形单元实现,按照FPGA内部的乘法器功能编写的-4-FFT butterfly-based unit to achieve, in accordance with the internal FPGA multiplier feature prepared Platform: |
Size: 1024 |
Author:苏菲 |
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Description: 信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。-FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems. Platform: |
Size: 308224 |
Author:卓智海 |
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Description: verilog实现的FFT变换,经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to Platform: |
Size: 618496 |
Author:culun |
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Description: alter官方fft程序 使用verilog编写 需要的同学可以下载-alter the official fft program uses verilog prepared students in need can be downloaded Platform: |
Size: 989184 |
Author:廖国杰 |
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Description: fftprocessing can complete 256 pointsFFT.-Hardware Description Language(HDL)is an advanced electronic designmethod.After HDL was put into use,it has draw great attention and gained popularity.The design used Verilog HDL and Schematic for entry tools having good effect in the system design,Meanwhile,it adopted the core provided by Xilinx/nc. improving the design efficiency.The whole design which is implemented inXC2S600E device relied on ISE and advanced hierarchy design mind.Furthermore,it is simulated and verified.The frequency attains to 40.64MHz.this paper aims at demonstration the applying FPGA to FFT signal processing can complete 256 pointsFFT. Platform: |
Size: 56320 |
Author:zzy |
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