Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fifo gray

Search list

[VHDL-FPGA-Verilog] yibufifo

Description: 详细说明异步fifo的设计 格雷码在地址的编码中的作用，及满空标志的产生-Detailed design of asynchronous fifo Gray code in the address of the code in effect and the emergence of Man flag
Platform: | Size: 238592 | Author: 刘留 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[Program doc] vhdlfi

Description: fifo vhdl源码，高可靠性，带有格雷码同步，有需要可依进行参考！-fifo vhdl source, high reliability, with Gray-code synchronization, there is a need-based reference!
Platform: | Size: 3072 | Author: lee | Hits:

[VHDL-FPGA-Verilog] fpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[VHDL-FPGA-Verilog] FIFO_Design

Description: 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
Platform: | Size: 90112 | Author: qwe | Hits:

[VHDL-FPGA-Verilog] fifo_ptrs_gray

Description: fifo pointers in verilog gray code utilization for synchronius
Platform: | Size: 3072 | Author: sljt | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 格雷码对地址编码的异步FIFO的实现方法-Gray code encoding to address the realization of the asynchronous FIFO method
Platform: | Size: 1024 | Author: hj | Hits:

[VHDL-FPGA-Verilog] GrayCounter2

Description: gray counter for async FIFO design
Platform: | Size: 1024 | Author: zismad | Hits:

[VHDL-FPGA-Verilog] FIFO_GRAY

Description:
Platform: | Size: 2048 | Author: elsa | Hits:

[VHDL-FPGA-Verilog] M2SDRAM_MR

Description: gray code based FIFO
Platform: | Size: 3072 | Author: 于强 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 一个FIFO产生程序，主要是一个格雷码的加法器-A FIFO generation process, is primarily a gray code adder
Platform: | Size: 5120 | Author: 洪琳琅 | Hits:

[Other] fifo-code

Description: Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
Platform: | Size: 3072 | Author: 王文 | Hits:

[VHDL-FPGA-Verilog] FIFO-and-CAM

Description: verilog code for gray counter,synchronous and asynchronous fifo
Platform: | Size: 25600 | Author: Abhijeet | Hits:

[VHDL-FPGA-Verilog] FPGA-FIFO

Description: FPGA-跨时钟域总线信号可靠传输异步FIFO技术安全可靠，格雷码计数，减少亚稳态-FPGA-clock domain crossing bus signals reliable transmission of asynchronous FIFO safe and reliable, Gray code count, reducing the metastable
Platform: | Size: 3072 | Author: 云平 | Hits:

[Other] fifo

Description: 异步FIFO实现 verilog代码，利用格雷码消除亚稳态-Asynchronous FIFO realize verilog code, Gray code to eliminate the use of metastable
Platform: | Size: 1024 | Author: 曹伟 | Hits:

[VHDL-FPGA-Verilog] FIFO.v

Description: 异步先进先出FIFO存储器，采用格雷码判定，消耗资源更小-Asynchronous FIFO FIFO memory, using Gray code determination, consume less resources
Platform: | Size: 1024 | Author: 张三 | Hits:

[Other] FIFO

Description: 关于异步FIFO的原码程序，采用格雷码改善了二进制码带来的不足- ON划词翻译ON实时翻译 On asynchronous FIFO the original code procedures, the use of gray code improves deficiency caused by binary code
Platform: | Size: 1024 | Author: 郭晓溪 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 同步fifo和异步fifo程序，含时钟同步。运用格雷码-Synchronous FIFO and asynchronous FIFO FIFO procedures, including clock synchronization. Application of gray code
Platform: | Size: 2048 | Author: zhaohongbing | Hits:

[VHDL-FPGA-Verilog] grey-code--FIFO-IP-core

Description: 基于格雷码的FIFO的IP核，调试可用于通信接口的队列传输。-Gray code based on FIFO IP core, debugging can be used for communication queue transmission interface.
Platform: | Size: 37888 | Author: 瞿盛 | Hits:

[VHDL-FPGA-Verilog] FIFO_ASY

Description: 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
Platform: | Size: 2048 | Author: 253765952 | Hits:
« 12 »

CodeBus www.codebus.net