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[Software Engineering] labQ2

Description: Source codes for verilog fifo for spartan 3
Platform: | Size: 252928 | Author: Krishna | Hits:

[VHDL-FPGA-Verilog] xapp460

Description: 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）-Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
Platform: | Size: 1594368 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] HighSpeedFIFOsInSpartan-IIFPGAs

Description: This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.
Platform: | Size: 30720 | Author: fjmwu | Hits:

[VHDL-FPGA-Verilog] based-on-Xilinx-PCIe-Core-DMA

Description: 1， 支持由板卡发起的DMA操作，既可以将板卡内的数据快速传输到PC，也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。 2， 利用Xilinx LogiCORE Endpoint Block Plus硬核，兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。 3， 在板卡的终端是标准的FIFO接口，可以接入各种形式的数据，例如AD采样数据，光纤数据，DA数据。 4， DriverStudio生成的驱动代码，最大限度的提高连续传输的速率，同时降低PC的负载。 5， 用户自定义BAR2空间，可用作自定义控制。 6， 支持32位和64位操作系统。
Platform: | Size: 2329600 | Author: rosen | Hits:

[VHDL-FPGA-Verilog] simple_spi_latest.tar

Description: - 与摩托罗拉的SPI规格兼容 - 增强摩托罗拉MC68HC11串行外设接口 - 4项深读FIFO - 4项深写入FIFO - 中断后1代，2，3或4个转移字节 - 8位WISHBONE RevB.3经典界面 - 经营的输入时钟频率范围广泛 - 静态同步设计 - 完全可合成 - 130LUTs在Spartan-II，230在ACEX LCELLs的-- Compatible with Motorola s SPI specifications - Enhanced Motorola MC68HC11 Serial Peripheral Interface - 4 entries deep read FIFO - 4 entries deep write FIFO - Interrupt generation after 1, 2, 3, or 4 transfered bytes - 8 bit WISHBONE RevB.3 Classic interface - Operates from a wide range of input clock frequencies - Static synchronous design - Fully synthesizable - 130LUTs in a Spartan-II, 230 LCELLs in an ACEX
Platform: | Size: 575488 | Author: 张居林 | Hits:

[VHDL-FPGA-Verilog] fifo_config

Description: This the fifo made fot Xilinx, spartan 3-This is the fifo made fot Xilinx, spartan 3
Platform: | Size: 4096 | Author: Petr | Hits:

[VHDL-FPGA-Verilog] ring_fifo

Description: use Sram with ring fifo Spartan-3
Platform: | Size: 3198976 | Author: lee | Hits:

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