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[Other resource] fifo

Description: 一个同步FIFO，包括testbench，
Platform: | Size: 1221 | Author: 张丰 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Other Embeded program] FIFO_v

Description: FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
Platform: | Size: 175104 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: | Size: 2048 | Author: 彭帅 | Hits:

[SCM] fifo

Description: 一个同步FIFO，包括testbench，-A synchronous FIFO, including the testbench,
Platform: | Size: 1024 | Author: 张丰 | Hits:

[VHDL-FPGA-Verilog] fifo1

Description: 异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been
Platform: | Size: 32768 | Author: 何勇 | Hits:

[VHDL-FPGA-Verilog] ascfifotestbench

Description: 自写异步 fifo TESTBench 该fifo对初学者很有帮助！-Since the write fifo TESTBench asynchronous fifo very helpful for beginners!
Platform: | Size: 66560 | Author: 丁昌圣 | Hits:

[Other] Memory

Description: Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
Platform: | Size: 846848 | Author: Lokous | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] asynfifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
Platform: | Size: 25600 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
Platform: | Size: 48128 | Author: 白桦 | Hits:

[VHDL-FPGA-Verilog] fifo_32_4321

Description: 用verilog写的输出数据宽度可变的FIFO,输入数据为32-bit，输出数据可以配置为4-1任意bit。有设计文件和testbench-Use verilog to write a variable width of the output data FIFO, input data for the 32-bit, output data can be configured as 4-1 arbitrary bit. There are design files and testbench
Platform: | Size: 5120 | Author: keven | Hits:

[VHDL-FPGA-Verilog] fifo64x8_tb

Description: Testbench for Xilinx 64x8 FIFO.
Platform: | Size: 1024 | Author: salman | Hits:

[VHDL-FPGA-Verilog] new_fifo

Description: 最新的testbench of FIFO ，使用Vmm，VCS，可以大致了解一下VMM的体系-the new fifo VMM testbench
Platform: | Size: 6144 | Author: niusl | Hits:

[VHDL-FPGA-Verilog] FifoAndTestbench

Description: 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
Platform: | Size: 2048 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] fifo_tb

Description: verilog implementation of 16X4 fifo with testbench
Platform: | Size: 1024 | Author: prateek | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 利用verilog来实现fifo的读写，并有testbench程序。-fifo verilog
Platform: | Size: 1024 | Author: meihanfei | Hits:

[VHDL-FPGA-Verilog] fifo

Description: actel 的同步硬件fifo的testbench,初学者可以看一下testbench怎么写的。-the testbench code of actel fpga,it is right for new learner~
Platform: | Size: 28672 | Author: 书荣 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步FIFO源代码，由模块调用自动生成，不包含测试向量。-Asynchronous FIFO source code automatically generated by the module calls, does not contain the testbench.
Platform: | Size: 2048 | Author: Yang Siyu | Hits:

[VHDL-FPGA-Verilog] fifo

Description: FIFO缓存器的设计及VHDL测试平台代码-FIFO buffer design and VHDL testbench code
Platform: | Size: 1790976 | Author: 叶宗英 | Hits:
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