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[Other resource] vhdl_fifo

Description: 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
Platform: | Size: 309997 | Author: 蔡庆重 | Hits:

[Other resource] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2661 | Author: nick | Hits:

[VHDL-FPGA-Verilog] vhdl_fifo

Description: 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
Platform: | Size: 309248 | Author: 蔡庆重 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[VHDL-FPGA-Verilog] vhdl0716

Description: ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.
Platform: | Size: 8431616 | Author: 杨奋燕 | Hits:

[VHDL-FPGA-Verilog] asyn_FIFOrealizedbyVHDL

Description: 一个比较经典的用VHDL实现的FIFO论文-Instance, the birthday of power wilt lift stamp cavity using VHDL wife of mother
Platform: | Size: 53248 | Author: Roger | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Platform: | Size: 6144 | Author: 刘义春 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger
Platform: | Size: 131072 | Author: 张星 | Hits:

[VHDL-FPGA-Verilog] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
Platform: | Size: 928768 | Author: alison | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[VHDL-FPGA-Verilog] fpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[VHDL-FPGA-Verilog] fifo-interface

Description: fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
Platform: | Size: 1024 | Author: sunbaoyu | Hits:

[Embeded-SCM Develop] afifo_0916

Description: 异步FIFO，使用XILINX产品实现，可以通过改参数来重新修改深度和位宽-Asynchronous FIFO, using the XILINX product realization, you can change parameters to re-modify the depth and Width
Platform: | Size: 154624 | Author: 范小虎 | Hits:

[VHDL-FPGA-Verilog] vhdlfifo1

Description: fifo - source code for first in first out(fifo) using VHDL
Platform: | Size: 1223680 | Author: nagarjuna reddy | Hits:

[VHDL-FPGA-Verilog] vhdlfifo

Description: fifo- source code for fifo using VHDL
Platform: | Size: 1223680 | Author: nagarjuna reddy | Hits:

[VHDL-FPGA-Verilog] fifo_vhdl

Description: FIFO using vhdl and aslo configurable
Platform: | Size: 7168 | Author: narayan | Hits:

[VHDL-FPGA-Verilog] async-FIFO

Description: 采用VHDL实现异步的FIFO程序，是学习FPGA的重点内容-VHDL implementation using asynchronous FIFO procedures, the key elements to learn FPGA! !
Platform: | Size: 220160 | Author: yihoumei | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 先进先出存储器的接口设计，采用VHDL语言-FIFO memory interface design, using VHDL language
Platform: | Size: 2466816 | Author: 凯一 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 设计一个同步的双端口fifo ,大小为8*128。-Designing a synchronous dual-port 8* 128 fifo using VHDL.
Platform: | Size: 35840 | Author: 沈湛 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用VHDL语言实现一种异步FIFO，并做时序仿真和功能仿真检验正确性。-Achieve an asynchronous FIFO using VHDL language, and do functional simulation and timing simulation test accuracy.
Platform: | Size: 504832 | Author: zk | Hits:
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