Search - fir quartus

[Other resource] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。
Platform: | Size: 909298 | Author: 王志 | Hits:

[VHDL-FPGA-Verilog] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233472 | Author: 杰轩 | Hits:

[VHDL-FPGA-Verilog] 66_FIR

Description: 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
Platform: | Size: 8192 | Author: 佴立峰 | Hits:

[matlab] fir_core

Description: fir滤波器，用matlab，dsp和quartus2设计的-fir filter, using Matlab, dsp design and quartus2
Platform: | Size: 95232 | Author: 吴涛 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 我自己用VHDL语言编的16阶FIR数字滤波器，仿真是在Quartus II上通过的，对大家一定有帮助的，压缩文件里还有详细的设计说明呢，肯定让你完全了解数字滤波器的设计。-VHDL language with my own series of 16-order FIR digital filter in the Quartus II simulation is adopted, the U.S. will certainly be helpful, compressed document also detailed design description, it certainly allows you to fully understand the digital filter设计.
Platform: | Size: 909312 | Author: 王志 | Hits:

[VHDL-FPGA-Verilog] VHDLFIR

Description: VHDL设计FIR滤波器基于QUARTUS和MATLAB-VHDL design of FIR filter based on Quartus and MATLAB
Platform: | Size: 1032192 | Author: twinslizzy | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[Other] DSP_yingyongjishu

Description: 现代DSP技术是西安电子科技大学的课件！有fft，fir，dspbulder，iir，quartus II 等内容，非常的详细，值得一看的好的ppt啊。我把好的资料贡献给大家看看啊1-Modern DSP technology is the Xi' an University of Electronic Science and Technology Courseware! There fft, fir, dspbulder, iir, quartus II and so on, very detailed, good to see ah ppt. Contribution to the information I give you a good look at ah 1
Platform: | Size: 25252864 | Author: 卢超 | Hits:

[VHDL-FPGA-Verilog] 1

Description: FIR的FPGA实现及其Quartus Ⅱ与MATLAB仿真 FIR的FPGA实现及其Quartus Ⅱ与MATLAB仿真-The FPGA realization of FIR and its Quartus Ⅱ and MATLAB simulation FIR realization of the FPGA and Quartus Ⅱ and MATLAB simulation
Platform: | Size: 175104 | Author: 南才北往 | Hits:

[Software Engineering] jifenlvboqi

Description: 为了解决软件无线电通信系统中频采样之后的极大数据量在基带处理部分对DSP计算的压力,常采用多速率处理技术.多速率处理过程中需要使用积分梳状滤波器、半带滤波器和高阶FIR滤波器.在分析了积分梳状滤波器的结构和特性的基础上,阐述了多级CIC滤波器一种高效的FPGA实现方法,该方法的正确性和可行性通过Quartus Ⅱ的时序仿真分析得以验证,实际中可以推广应用.-In order to solve software-defined radio communications system after IF sampling of great amount of data to the DSP in the baseband processor part of the calculation of the pressure, often using multi-rate processing technology. Multi-rate processing need to use the integrator comb filter, half-band filters and high-order FIR filter. in the analysis of the integrator comb filter structure and characteristics, based on the multi-stage CIC filter described an efficient FPGA implementations, the correctness and feasibility of the method adopted by the timing Quartus Ⅱ simulation analysis can be verified in practice can be applied.
Platform: | Size: 180224 | Author: 王楚宏 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Platform: | Size: 352256 | Author: hongwan | Hits:

[VHDL-FPGA-Verilog] Crack_QII81_FULL_License

Description: quartus 8.1 ipcore lic,包含ddr、ddr2、fir、nco-quartus 8.1 ipcore lic, with ddr, ddr2, fir, nco
Platform: | Size: 29696 | Author: wcm | Hits:

[Program doc] daima

Description: fir滤波器的代码实现，最好使用quartus ii开发工具-Fir filter code realization, had better use quartus ii development tools
Platform: | Size: 12288 | Author: 王晶 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 真正意思上的fir滤波器课程设计，基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases
Platform: | Size: 1439744 | Author: liyu | Hits:

[VHDL-FPGA-Verilog] fir-and-iir

Description: FPGA关于数字滤波器设计,FIR的FPGA实现及其Quartus与MATLAB仿真-FPGA on the digital filter design, FIR s Quartus FPGA Implementation and Simulation with MATLAB
Platform: | Size: 5149696 | Author: 方明 | Hits:

[VHDL-FPGA-Verilog] fir(1)

Description: 基于fpga的fir数字滤波器的设计的用QUARTUS II 做的VHDL语言的源代码-The fir fpga based design of digital filters QUARTUS II to do with the source code for VHDL,
Platform: | Size: 988160 | Author: 郑晓坚 | Hits:

[matlab] MATLAB-and-Quartus

Description: 本资料是以matlab与quartus软件综合开发出一个FIR数字滤波器，对硬件电路的设计有很大帮助。-This information is based on comprehensive development of the software matlab with quartus a FIR digital filter, the hardware design of the circuit of great help.
Platform: | Size: 253952 | Author: wxm27811 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: Quartus II中滤波器的设计，里面含有高通滤波器，低通滤波器，带阻滤波器，主要用于滤除心电信号中的干扰-Quartus II filter design, which contains a high-pass filter, low-pass filter, band stop filter, mainly used for filtering of ECG signal interference
Platform: | Size: 3363840 | Author: | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 低通、十阶FIR滤波器，Quartus II开发环境。-Low pass, ten-order FIR filter, Quartus II development environment.
Platform: | Size: 4159488 | Author: peter | Hits:

[VHDL-FPGA-Verilog] fir-ip-vhdl

Description: altera quartus fir ip核 vhdl程序含测试文件-altera quartus fir ip nuclear vhdl program including test files
Platform: | Size: 3072 | Author: bambod | Hits:

« 12 3 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Other resource] fir

[VHDL-FPGA-Verilog] 100个vhdl设计例子

[VHDL-FPGA-Verilog] 66_FIR

[matlab] fir_core

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] VHDLFIR

[Other] VerilogHDL

[Other] DSP_yingyongjishu

[VHDL-FPGA-Verilog] 1

[Software Engineering] jifenlvboqi

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] Crack_QII81_FULL_License

[Program doc] daima

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] fir-and-iir

[VHDL-FPGA-Verilog] fir(1)

[matlab] MATLAB-and-Quartus

[VHDL-FPGA-Verilog] FIR

[VHDL-FPGA-Verilog] FIR

[VHDL-FPGA-Verilog] fir-ip-vhdl

CodeBus www.codebus.net