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[OtherMPCOL_2005NOV10_INT_AN_28

Description: FIR Filter Coefficient Design Examples For the AFEDRI8201 in Digital Radio-FIR Filter Design Examples Fo r AFEDRI8201 in the Digital Radio
Platform: | Size: 104077 | Author: 李鸿 | Hits:

[Web Servertrial4

Description: 求出laguerre滤波器的分子分母系数,绘出其幅频响应图并与FIR滤波器作比较。该程序为19阶Laguerre低通滤波器和22阶带通滤波器-obtained laguerre filter coefficient of molecular denominator, chart its amplitude frequency response plans with the FIR filter for comparison. The procedure for the 19-Laguerre low-pass filter and 22 band pass filter
Platform: | Size: 1312 | Author: 吉芳芳 | Hits:

[Other resourcecoef_reload72

Description: Coefficient Reload FIR Filter Design Example v7.2
Platform: | Size: 64964 | Author: 邱应强 | Hits:

[OtherMPCOL_2005NOV10_INT_AN_28

Description: FIR Filter Coefficient Design Examples For the AFEDRI8201 in Digital Radio-FIR Filter Design Examples Fo r AFEDRI8201 in the Digital Radio
Platform: | Size: 103424 | Author: 李鸿 | Hits:

[WEB Codetrial4

Description: 求出laguerre滤波器的分子分母系数,绘出其幅频响应图并与FIR滤波器作比较。该程序为19阶Laguerre低通滤波器和22阶带通滤波器-obtained laguerre filter coefficient of molecular denominator, chart its amplitude frequency response plans with the FIR filter for comparison. The procedure for the 19-Laguerre low-pass filter and 22 band pass filter
Platform: | Size: 1024 | Author: 吉芳芳 | Hits:

[VHDL-FPGA-Verilog8stepSymmetryCoefficientFilter

Description: 8阶对称系数并行FIR滤波器(verilog)用作数字滤波,系数可调。根据实际截止频率决定。-8-order FIR filter symmetric coefficients parallel (verilog) used for digital filtering, adjustable coefficient. Decisions based on the actual cut-off frequency.
Platform: | Size: 1024 | Author: TGY | Hits:

[DSP programfir

Description: 有限冲激响应滤波器FIR的设计。采用c语言设计。系数由matlab计算得到。可在CCS环境中采用DSPs(0TMS320C5402)来实现。-Finite Impulse Response FIR filter design. Design using c language. Coefficient calculated by matlab. Can be used in the CCS environment DSPs (0TMS320C5402) to realize.
Platform: | Size: 1024 | Author: 颜新卉 | Hits:

[matlabadaptivefir

Description: 自适应滤波器。自适应滤波器为11个权系数的FIR结构。(1)不同的方差σ2(2)LMS算法画出一次实验的误差平方收敛曲线,训练长度为500,给出滤波器系数;进行20次独立实验,给出平均收敛曲线。不同步长值的比较。(3)RLS算法,LMS和RLS算法的比较 -Adaptive filter. Adaptive filter weights for 11 of the FIR structure. (1) different variance σ2 (2) LMS algorithm for an experiment to draw square error convergence curve, the training length is 500, given filter coefficient conduct 20 independent experiments, given the average convergence curve. Are not synchronized long value comparison. (3) RLS algorithm, LMS and RLS Algorithms
Platform: | Size: 5120 | Author: 梁上泉 | Hits:

[VHDL-FPGA-Verilogfirshuzilvboqi

Description: :介绍了基于FPGA的FIR数字滤波器的设计与实现,该设计利用Matlab工具箱设计窗函数计算FIR滤波器系数,并通过VHDL层次化设计方法,同时FPGA与单片机有机结合,采用C51及VHDL语言模块化的设计思想及进行优化编程,有效实现了键盘可设置参数及LCD显示。结果表明此实现结构能进一步完善数据的快速处理和有效控制,提高了设计的灵活性、可靠性和功能的可扩展性。 -: This paper presents FPGA-based FIR digital filter design and realization of the design using Matlab toolbox window function designed FIR filter coefficient calculation, and through VHDL hierarchical design methodology, FPGA and MCU at the same time the organic combination of the use of C51 and VHDL language modular design concepts and optimize the programming, the effective realization of the keyboard to set the parameters and the LCD display. The results show that this structure can be further improved to achieve rapid data processing and effective controls, improved design flexibility, reliability and scalability features.
Platform: | Size: 7168 | Author: 佘斌 | Hits:

[Mathimatics-Numerical algorithmsezfir16

Description: FIR滤波器系数生成,可供DSP软件编程使用-FIR filter coefficient generated for the use of DSP software programming
Platform: | Size: 1024 | Author: zzr | Hits:

[CommunicationDigitalEqualizer

Description: After the run of the "MyEqualizer.m" file a graphical user interface appear. By pressing the "Load" we can load audio signal (type .wmv). After we can model the frequency behavior of the FIR filter that is used to filter that signal. After we can listen the filtred audio signal by pressing the "Play " button. In the GUI M-file I m using three importanat function: [ ]=coeff() that generate cell contain the coefficient of the equalizer, equalizer_plot() who plot the frequency behavior of equalizer and the equalizer_play who filter and play the filtered audio signal.
Platform: | Size: 1456128 | Author: Nafiou | Hits:

[DSP programFIR

Description: 线性缓冲区FIR滤波器设计,可利用MATLAB产生系数,利用CCS开发环境,调试成功!-FIR filter design for linear buffer can be generated using MATLAB coefficient, the use of CCS development environment, debugging success!
Platform: | Size: 5120 | Author: guyue | Hits:

[OtherFIR_csd_mul

Description: 采用CSD编码的常系数乘法器的FIR滤波器的设计。-CSD-coded using constant coefficient multipliers of the FIR filter design.
Platform: | Size: 9216 | Author: 敬礼 | Hits:

[Waveletfir

Description: FIR函数通过定义的系数和延时线来实现有限脉冲响应FIR滤波器。该函数产生了对输入数据的响应。该过滤器(通带,阻带等特点)由系数和抽头数决定。-FIR function by defining the coefficients and delay line to achieve the finite impulse response FIR filter. The function of the input data generated response. The filter (passband, stopband and so on) coefficient and the number of taps by the decision.
Platform: | Size: 3072 | Author: niky | Hits:

[Communication-Mobilefir

Description: 3. 用VC编程浮点程序实现对语音信号的按帧滤波。 1) 在主程序中读取FIR DF系数文件。 2) 在主程序中按帧读取语音样点文件,每帧180点。 3) 设计浮点滤波子程序,供主程序调用。 4) 保存滤波结果数据到文件中。 5) 用cooledit试听滤波后的语音信号。 -3. VC programming with floating-point program to realize the speech signal by frame filtering. 1) In the main program file to read FIR DF coefficient. 2) The main program reads the voice samples according to the frame files, 180 points per frame. 3) floating-point filter design routines for the main program calls. 4) save the filtered data to the file. 5) Listen with cooledit voice signal after filtering.
Platform: | Size: 2813952 | Author: 陈永尧 | Hits:

[VHDL-FPGA-Verilogfir-filter

Description: 11阶fir数字滤波器的verilog程序设计,线性相位,系数量化处理-11 order of fir digital filter verilog programming, linear phase, the coefficient quantization
Platform: | Size: 59392 | Author: happy | Hits:

[VHDL-FPGA-Verilog32-order-FIR-on-FPGA

Description: 基于FPGA的32阶FIR滤波器设计,研究了一种采用FPGA实现数字滤波器硬件电路方案;讨论了窗函数的选择、滤波器的结构以及系数量化问题-32 order FIR filter design based on FPGA, an FPGA implementation digital filter hardware circuit program discussed the choice of the window function, the structure of the filter coefficient quantization problem
Platform: | Size: 240640 | Author: 沧海一粟 | Hits:

[matlabmatlab3

Description: Dumps FIR filter coefficient vector to file in C language format in forward order. Creates two files "filename.h" which defines the size of the array and declares the array as extern, and "filename.c" which contains the instance of the array variable. The coefficients are stored as Q format numbers-Dumps FIR filter coefficient vector to file in C language format in forward order. Creates two files "filename.h" which defines the size of the array and declares the array as extern, and "filename.c" which contains the instance of the array variable. The coefficients are stored as Q format numbers
Platform: | Size: 1024 | Author: bernibml | Hits:

[Otherfilter

Description: 产生输入FSK信号的程序 FIR滤波器设计程序 IIR滤波器设计程序 FIR滤波器实现程序(用滤波器系数对输入信号进行滤波) IIR滤波器实现程序(用滤波器系数对输入信号进行滤波)-FSK input signal generating program FIR filter design procedures IIR filter design procedures FIR filter (with the filter coefficient for filtering the input signal) IIR filter is implemented (with the filter coefficient for filtering the input signal)
Platform: | Size: 1024 | Author: 王瑞琰 | Hits:

[VHDL-FPGA-Verilog滤波器实验报告

Description: 设计一个 1MHz 的 FIR 低通滤波器。 要求: ① 时钟信号频率 16MHz; ② 输入信号位宽 8bits,符号速率 16MHz ③ 要求在 Matlab 软件中进行 FIR 滤波器浮点和定点仿真,并确定 FIR 滤波器抽头系数 ④ 写出测试仿真程序。(Design a 1MHz FIR low pass filter. Requirements: (1) clock signal frequency 16MHz; (2) input signal bit width of 8bits, symbol rate of 16MHz Requirements in Matlab FIR filter floating-point and fixed-point simulation, and determine the FIR filter tap coefficient (4) write the test simulation program.)
Platform: | Size: 342016 | Author: 羊羊驼 | Hits:
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