Search - fir filter implementation in verilog

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[DSP program] TMS320C54x DSP 的cpu和外围设备 DL : 0: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Update : 2025-02-17 Size : 1.36mb Publisher : 呈一
[VHDL-FPGA-Verilog] coeff_rom_3_4 DL : 0: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Update : 2025-02-17 Size : 2kb Publisher : surya
[VHDL-FPGA-Verilog] fir_lms DL : 0: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Update : 2025-02-17 Size : 12kb Publisher : 田文军
[Other] FIR DL : 0: This implementation of Low power Finite Impulse response filter design and implemented in Verilog-This is implementation of Low power Finite Impulse response filter design and implemented in Verilog
Update : 2025-02-17 Size : 5kb Publisher : Ravindra
[VHDL-FPGA-Verilog] fir DL : 0: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Update : 2025-02-17 Size : 3.17mb Publisher : de de
[VHDL-FPGA-Verilog] HalfbandDec DL : 0: 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
Update : 2025-02-17 Size : 1kb Publisher : 小梦
[Other] proiect DL : 0: Fir filter implemented in verilog and tasted. also conteins the implementation in simulink
Update : 2025-02-17 Size : 1.76mb Publisher : valentina199114
[Other Embeded program] FIR32 DL : 1: 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
Update : 2025-02-17 Size : 3kb Publisher : Awei
[VHDL-FPGA-Verilog] FIR设计实现sgh DL : 0: FIR滤波FPGA实现，已在仿真软件上验证实现，不是IP核，不是ip核。(FIR filter FPGA implementation, has been verified in the simulation software, not IP core, not IP core.)
Update : 2025-02-17 Size : 25kb Publisher : 韩冻少