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[VHDL-FPGA-Verilog] 8stepSymmetryCoefficientFilter

Description: 8阶对称系数并行FIR滤波器(verilog)用作数字滤波，系数可调。根据实际截止频率决定。-8-order FIR filter symmetric coefficients parallel (verilog) used for digital filtering, adjustable coefficient. Decisions based on the actual cut-off frequency.
Platform: | Size: 1024 | Author: TGY | Hits:

[VHDL-FPGA-Verilog] fir_using_FPGA

Description: 基于verilog的fir滤波，并带matlab仿真-Verilog-based filtering of fir and bring matlab simulation
Platform: | Size: 24576 | Author: 宇天 | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[Program doc] DSP--base--on-FPGA

Description: 这是一本国外的经典教材，讲述了现阶段所有数字信号处理的FPGA实现，从第二章讲述二进制的算法到现阶段数字信号处理的研究热点，基于FPGA实现！包括FIR，自适应滤波，纠错码，调制解调，加密，傅立叶变换等等。更难能可贵的是每个例子都有VHDL和Verilog代码-This is a classic foreign materials, described at this stage all the digital signal processing FPGA, from the second chapter about the binary digital signal processing algorithms to the current stage of research focus, based on FPGA implementation! Including FIR, adaptive filtering, error-correcting codes, modulation and demodulation, encryption, Fourier transform and so on. Even more valuable is that each case has a VHDL and Verilog code! !
Platform: | Size: 7067648 | Author: 刘伟 | Hits:

[VHDL-FPGA-Verilog] dilbalu_fir7

Description: basic fir filtering in verilog fpga in vhdl
Platform: | Size: 142336 | Author: dileepkumar | Hits:

[VHDL-FPGA-Verilog] HalfbandDec

Description: 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
Platform: | Size: 1024 | Author: 小梦 | Hits:

[VHDL-FPGA-Verilog] rc_flt

Description: 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validation, using verilog language.
Platform: | Size: 4096 | Author: 小梦 | Hits:

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