Description: vhdl语言编写的复数乘法运算器原代码,采用定点运算,并将复数乘法转为实数运算。-VHDL language in the plural multiplication with the original code using fixed-point computation. will the plural multiplication to real operations. Platform: |
Size: 1275 |
Author:susu |
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Description: vhdl语言编写的复数乘法运算器原代码,采用定点运算,并将复数乘法转为实数运算。-VHDL language in the plural multiplication with the original code using fixed-point computation. will the plural multiplication to real operations. Platform: |
Size: 1024 |
Author:susu |
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Description: 对一般的PLL及APLL,定点PLL进行了MATLAB SIMULINK仿真,可以由程序直接生成PLL的VHDL和C源代码-General PLL and APLL, fixed-point MATLAB SIMULINK a PLL simulation, can be directly generated by the PLL of VHDL and C source code Platform: |
Size: 398336 |
Author:joshua |
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Description: 此代码用于实现基2的SRT除法器设计,可以实现400MHz以上的32位定点无符号数除法器(除数、被除数和余数均由16位整数和16位小数组成,商由32位整数和16位小数构成,包括源代码和测试文件,可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation. Platform: |
Size: 2048 |
Author:朱秋玲 |
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Description: 设计定点寄存器的好书,希望大家喜欢,对哦多交流-Design of fixed-point register books, I hope you like it, oh, more exchanges of Platform: |
Size: 381952 |
Author:tianzhen |
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Description: 是codic算法实现atan的C程序,包括定点和浮点程序,已经通过验证。-Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated. Platform: |
Size: 3072 |
Author:张堃 |
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Description: 本文提出了加快发展之路
从理论设计,通过Matlab / Simulink环境
在定点算法对其行为模拟的
在FPGA或定制实现硅片。这个了
实现了netlist移植的Simulink系统
描述成的硬件描述语言[VHDL]。在这个例子中,这个
Simulink-to-VHDL转换器被设计来使用
代码来描述结构VHDL系统互连,
允许简单的行为说明基本模块。
结果VHDL bit-true交付后代码
比较定点Simulink仿真模型等效
模拟。-This paper presents the way of speeding up the route
from the theoretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
description into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descriptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations. Platform: |
Size: 147456 |
Author:王晓 |
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Description: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
and more sevear is such distortion is random.
To handle this, multipath affected channels require Equalizers at receaver end.
such equalizer uses different learning Algorithms for identifying channels continuously.
This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton
It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic. Platform: |
Size: 14336 |
Author:Arun |
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Description: 用VHDL语言编写的带有闹钟功能的数字时钟,可实现定时定点闹钟。-Written in VHDL, digital clock with alarm function can be realized fixed-point alarm regularly. Platform: |
Size: 1024 |
Author:汤双泽 |
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Description: This paper presents the way of speeding up the route
from the oretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
description into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descriptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations.-This paper presents the way of speeding up the route
from the theoretical design with Simulink/Matlab, via
behavioral simulation in fixed-point arithmetic to the
implementation on either FPGA or custom silicon. This has
been achieved by porting the netlist of the Simulink system
description into the VHDL. At the first instance, the
Simulink-to-VHDL converter has been designed to use
structural VHDL code to describe system interconnections,
allowing simple behavioral descriptions for basic blocks.
The resulting VHDL code delivers bit-true result when
compared to the equivalent fixed-point Simulink model
simulations. Platform: |
Size: 147456 |
Author:jack |
Hits: