Search - fixed point vhdl

Search - fixed point vhdl - List

[Communication] ccmulVHDL DL : 0: vhdl语言编写的复数乘法运算器原代码，采用定点运算，并将复数乘法转为实数运算。-VHDL language in the plural multiplication with the original code using fixed-point computation. will the plural multiplication to real operations.
Update : 2008-10-13 Size : 1.25kb Publisher : susu
[Communication] ccmulVHDL DL : 0: vhdl语言编写的复数乘法运算器原代码，采用定点运算，并将复数乘法转为实数运算。-VHDL language in the plural multiplication with the original code using fixed-point computation. will the plural multiplication to real operations.
Update : 2025-02-19 Size : 1kb Publisher : susu
[Post-TeleCom sofeware systems] Phase_Locked_Loop DL : 0: 对一般的PLL及APLL,定点PLL进行了MATLAB SIMULINK仿真，可以由程序直接生成PLL的VHDL和C源代码-General PLL and APLL, fixed-point MATLAB SIMULINK a PLL simulation, can be directly generated by the PLL of VHDL and C source code
Update : 2025-02-19 Size : 389kb Publisher : joshua
[VHDL-FPGA-Verilog] divider DL : 1: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Update : 2025-02-19 Size : 2kb Publisher : 朱秋玲
[VHDL-FPGA-Verilog] FFT-FPGA DL : 0: 16位定点FFT-DSP的FPGA实现，相关代码和实用说明-16-bit fixed-point FFT-DSP realize the FPGA, the relevant code and practical description
Update : 2025-02-19 Size : 3.66mb Publisher : 杨合
[Windows Develop] desingofmultiply DL : 0: 设计定点寄存器的好书，希望大家喜欢，对哦多交流-Design of fixed-point register books, I hope you like it, oh, more exchanges of
Update : 2025-02-19 Size : 373kb Publisher : tianzhen
[Other] mux8 DL : 0: 定点八位乘法器的原理图设计，已通过功能仿真！-8 fixed-point multiplier schematic design, functional simulation has passed!
Update : 2025-02-19 Size : 403kb Publisher : lxp
[VHDL-FPGA-Verilog] tAtan2Cordic DL : 0: 是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。-Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.
Update : 2025-02-19 Size : 3kb Publisher : 张堃
[Software Engineering] matlab_to_vhdlfpga DL : 0: 　　本文提出了加快发展之路　　从理论设计,通过Matlab / Simulink环境　　在定点算法对其行为模拟的　　在FPGA或定制实现硅片。这个了　　实现了netlist移植的Simulink系统　　描述成的硬件描述语言[VHDL]。在这个例子中,这个　　Simulink-to-VHDL转换器被设计来使用　　代码来描述结构VHDL系统互连, 　　允许简单的行为说明基本模块。　　结果VHDL bit-true交付后代码　　比较定点Simulink仿真模型等效　　模拟。-This paper presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.
Update : 2025-02-19 Size : 144kb Publisher : 王晓
[VHDL-FPGA-Verilog] 16bitFFTFPGA DL : 0: 16位定点FFT-DSP的FPGA实现(相关代码和使用说明)-16-bit fixed-point FFT-DSP implementation of the FPGA (the relevant codes and instructions)
Update : 2025-02-19 Size : 3.57mb Publisher : tanghongwu
[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar DL : 0: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Update : 2025-02-19 Size : 14kb Publisher : Arun
[VHDL-FPGA-Verilog] chufaqichengxu DL : 0: 除法器程序，除法器模块，定点数除法的相关代码。-Divider procedures, divider module, the related fixed-point code division.
Update : 2025-02-19 Size : 383kb Publisher : jiachen
[Software Engineering] clock1 DL : 0: 用VHDL语言编写的带有闹钟功能的数字时钟，可实现定时定点闹钟。-Written in VHDL, digital clock with alarm function can be realized fixed-point alarm regularly.
Update : 2025-02-19 Size : 1kb Publisher : 汤双泽
[VHDL-FPGA-Verilog] fix2float_signed DL : 0: VHDL语言，有符号定点数转化为浮点数，Pavle Belanovic教授编写-Conversion from signed fixed-point to floating-point representation
Update : 2025-02-19 Size : 3kb Publisher : 刘畅
[VHDL-FPGA-Verilog] arraymultiplier DL : 0: vhdl code,about arraymultiplier,fixed point
Update : 2025-02-19 Size : 1kb Publisher : esther
[Other] multiplier8x8 DL : 0: 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
Update : 2025-02-19 Size : 2kb Publisher : superbear
[VHDL-FPGA-Verilog] vhdl-floating-pt DL : 0: code for fixed & floating point-code for fixed & floating point........
Update : 2025-02-19 Size : 19kb Publisher : nagesh
[VHDL-FPGA-Verilog] Simulink-to-VHDL-Route DL : 0: This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.-This paper presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.
Update : 2025-02-19 Size : 144kb Publisher : jack
[Algorithm] divider DL : 0: 16位定点无符号数除法器，除数、被除数均由16位整数和16位小数组成，商由32位整数和16位小数构成，余数由32位小数组成-Unsigned 16-bit fixed-point divider, divisor, dividend by 16-bit integer and 16 fractional bits, commercial 32-bit integer and 16 by the decimal form, the remainder from 32 fractional bits
Update : 2025-02-19 Size : 1kb Publisher : liuyi
[Windows Develop] fixed-point-sqrt_latest.tar DL : 0: Code source d une solution pour calculer la racine carre en VHDL
Update : 2025-02-19 Size : 21kb Publisher : deka

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