Search - floating point

[Other resource] Floating-point-complex-radix-2-decimation-in-time-

Description: 浮点复数基2时分FFT完成适当的FFT，输出改写输入缓冲器。-floating-point complex FFT-based two hours to complete the FFT output rewritten input buffer.
Platform: | Size: 1440 | Author: minytian | Hits:

[Other resource] Fast Floating-Point Arithmetic Emulation on the Bl

Description: ADI BF 16位定点DSP的快速浮点仿真的汇编代码-ADI BF 16-bit fixed point DSP fast floating point simulation code compilation
Platform: | Size: 19010 | Author: 李里 | Hits:

[DSP program] Fast Floating-Point Arithmetic Emulation on the Bl

Description: ADI BF 16位定点DSP的快速浮点仿真的汇编代码-ADI BF 16-bit fixed point DSP fast floating point simulation code compilation
Platform: | Size: 18432 | Author: | Hits:

[VHDL-FPGA-Verilog] flowadd

Description: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Platform: | Size: 1024 | Author: 张桓铭 | Hits:

Description: 各种51单片机源程序集，包括浮点数的计算，多字节的加减等算法的实现-SCM source scripts, including floating point calculations, multi-byte such as addition and subtraction algorithm implementation
Platform: | Size: 125952 | Author: 周云 | Hits:

[VHDL-FPGA-Verilog] vhdldesign

Description: 浮点加法器的VHDL算法设计浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
Platform: | Size: 202752 | Author: yan | Hits:

[Algorithm] Floating-point-complex-radix-2-decimation-in-time-

Description: 浮点复数基2时分FFT完成适当的FFT，输出改写输入缓冲器。-floating-point complex FFT-based two hours to complete the FFT output rewritten input buffer.
Platform: | Size: 1024 | Author: minytian | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 利用FPGA实现浮点运算的verilog代码希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Platform: | Size: 130048 | Author: jake | Hits:

[Other Embeded program] 03_Quantization

Description: This lab exercise will introduce you to AccelDSP’s floating- to fixed-point conversion features. AccelDSP will automatically generate a fixed-point representation of a floating-point design. This process is controllable by using quantize directives.-This lab exercise will introduce you to Acc elDSP's floating-to fixed-point conversion f eatures. AccelDSP will automatically generat e a fixed-point representation of a floating-p oint design. This process is controllable by us ing quantize directives.
Platform: | Size: 26624 | Author: 杨平 | Hits:

[Other] dsp-fixed-point-computation

Description: 该文档主要讲述dsp芯片中进行定点运算所设计的基本问题，分别介绍了定标、从浮点到定点的运算，定点的快速运算及其实现。文档中举出大量的例子说明，相信下载阅读后肯定会很有收获。-the document focuses on the dsp chip sentinel operation designed the basic problem introduced calibration, from floating-point to fixed-point arithmetic, fixed-point operations and the rapid realization. Documents cite a lot of examples, I believe that after reading the download will certainly learned a great deal.
Platform: | Size: 270336 | Author: 王大雷 | Hits:

[assembly language] ieee_matrix

Description: 用汇编写的矩阵乘法和IEEE浮点数转换 -was compiled using the matrix multiplication and IEEE floating point conversion
Platform: | Size: 3072 | Author: zy | Hits:

[OS program] div2

Description: 大数除法的实现算法，不仅能实现两个大数的除法，而且能实现浮点数之间以及浮点数与整数之间的除法-majority of the division algorithm, is not only able to make large numbers of division two, but to achieve a float and between integer and floating point divider between the
Platform: | Size: 241664 | Author: 赵惠 | Hits:

[SCM] ieee754c

Description: 浮点和16进制互相转换软件。用于单片机调试，浮点-定点转换，我在开发中经常用到。很不错的软件。-Hexadecimal floating-point and 16 co-conversion software. For single-chip debug, floating-point- fixed-point conversion, I frequently used in the development. Very good software.
Platform: | Size: 8192 | Author: wangshen | Hits:

[Software Engineering] AccelDSP

Description: AccelDSP Synthesis Tool Floating-Point to Fixed-Point Conversion of MATLAB Algorithms Targeting FPGAs
Platform: | Size: 300032 | Author: hesonwhb | Hits:

[Embeded-SCM Develop] fsqr

Description: 功能：浮点数开平方（快速逼近算法）入口条件：操作数在[R0]中。出口信息：OV=0时，平方根仍在[R0]中，OV=1时，负数开平方出错。影响资源：PSW、A、B、R2～R7 堆栈需求：２字节 -Features: Floating-point square root (fast approximation algorithm) entrance conditions: operand in [R0] in. Export information: OV = 0 when the square root is still [R0] in, OV = 1, the negative square root error. The impact of resources: PSW, A, B, R2 ~ R7 Stack requirements: 2 bytes
Platform: | Size: 4096 | Author: kos | Hits:

[VHDL-FPGA-Verilog] floating-point-adder1

Description: 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
Platform: | Size: 9216 | Author: Rosen | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] floating-point-adder

Description: verilog implementation of the floating point adder
Platform: | Size: 2048 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] floating-point-multiplier

Description: verilog implementation of the floating point multiplier
Platform: | Size: 1024 | Author: ramtin | Hits:

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