Search - floating point in verilog

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[Other resource] fpu DL : 0: 利用FPGA实现浮点运算的verilog代码希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Update : 2008-10-13 Size : 127.09kb Publisher : jake
[Other resource] flowadd DL : 0: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Update : 2008-10-13 Size : 1.41kb Publisher : 张桓铭
[VHDL-FPGA-Verilog] flowadd DL : 0: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Update : 2025-02-17 Size : 1kb Publisher : 张桓铭
[VHDL-FPGA-Verilog] fpu DL : 0: 利用FPGA实现浮点运算的verilog代码希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Update : 2025-02-17 Size : 127kb Publisher : jake
[VHDL-FPGA-Verilog] Lattice_Verilog DL : 0: 本文讨论了AR模型及线性预测的原理，在浮点型DSP TMS320C6713B上实现了语音信号线性预测系数(LPC)的提取，并利用LPC系数用Verilog语言实现了AR模型的Lattice结构。-This article discusses the AR model and the principle of linear prediction, in the floating-point DSP TMS320C6713B realize the voice signal on the linear prediction coefficient (LPC) of the extract, and the use of LPC coefficients using Verilog languages realize the AR model Lattice structure.
Update : 2025-02-17 Size : 14kb Publisher : 万金油
[VHDL-FPGA-Verilog] fadd DL : 0: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Update : 2025-02-17 Size : 2kb Publisher : 兰兰
[Linux-Unix] fpadd DL : 0: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Update : 2025-02-17 Size : 12kb Publisher : 孟军
[VHDL-FPGA-Verilog] fpu100_latest.tar DL : 1: 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.
Update : 2025-02-17 Size : 1.89mb Publisher : 赵恒
[VHDL-FPGA-Verilog] floating_point_addition_subtraction DL : 0: Simple floating point addition unit written in Verilog
Update : 2025-02-17 Size : 3kb Publisher : binh
[VHDL-FPGA-Verilog] Floating-Point-Adder DL : 0: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Update : 2025-02-17 Size : 151kb Publisher : 凌音
[VHDL-FPGA-Verilog] CourseDesign DL : 0: 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
Update : 2025-02-17 Size : 240kb Publisher : 李伟彬
[VHDL-FPGA-Verilog] fpufiles DL : 0: floating point adder mul and sub in verilog code
Update : 2025-02-17 Size : 19kb Publisher : khosro raja
[VHDL-FPGA-Verilog] canbus DL : 0: CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
Update : 2025-02-17 Size : 843kb Publisher : 张小琛
[VHDL-FPGA-Verilog] sqrt_for_single_float_point DL : 0: 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
Update : 2025-02-17 Size : 5kb Publisher : 楚艳超
[VHDL-FPGA-Verilog] campur DL : 0: total added value for 6 data in 32bit floating point for verilog code
Update : 2025-02-17 Size : 3kb Publisher : hafiez
[VHDL-FPGA-Verilog] count-for-6-data DL : 0: count data entry for 6 data and convert to 32bit floating point in verilog code.
Update : 2025-02-17 Size : 1kb Publisher : hafiez
[VHDL-FPGA-Verilog] Floating-Point-Multiplier-in-Verilog DL : 0: Floating Point Multiplier in Verilog
Update : 2025-02-17 Size : 63kb Publisher : Khalid Nawaz Khan
[VHDL-FPGA-Verilog] eetop.cn_利用FPGA实现浮点运算的verilog代码 DL : 0: 计算机里整数和小数形式就是按普通格式进行存储，例如1024、3.1415926等等，这个没什么特点，但是这样的数精度不高，表达也不够全面，为了能够有一种数的通用表示法，就发明了浮点数。浮点数的表示形式有点像科学计数法（*.*****×10^***），它的表示形式是0.*****×10^***，在计算机中的形式为 .***** e ±***），其中前面的星号代表定点小数，也就是整数部分为0的纯小数，后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数，例如1024就能表示成0.1024×10^4，也就是 .1024e+004，3.1415926就能表示成0.31415926×10^1，也就是 .31415926e+001，这就是浮点数。浮点数进行的运算就是浮点运算。浮点运算比常规运算更复杂，因此计算机进行浮点运算速度要比进行常规运算慢得多。(Floating point representation is a bit like scientific notation (*.***** * 10^***), its representation is 0.***** * 10^*** in the computer in the form of.***** e +, * * *) in front of the asterisk represents fixed-point decimal, which is part of the 0 pure decimal integer index, part of the back is a fixed integer. In this way, any integer and decimal can be expressed. For example, 1024 can be expressed as 0.1024 * 10^4, that is,.1024e+004, 3.1415926 can be expressed as 0.31415926 * 10^1, that is.31415926e+001, that is the floating point number. The operation of floating-point numbers is floating point operation.)
Update : 2025-02-17 Size : 127kb Publisher : 哒啦啦啦
[Other] 基于FPGA的单精度浮点数乘法器设计 DL : 0: 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.)
Update : 2025-02-17 Size : 2.32mb Publisher : sisuozheweilai
[VHDL-FPGA-Verilog] float_mult32x32.v DL : 0: verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)
Update : 2025-02-17 Size : 1kb Publisher : orangell

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