Search - floating point adder verilog HDL

[Linux-Unix] fpadd

Description: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Platform: | Size: 12288 | Author: 孟军 | Hits:

[VHDL-FPGA-Verilog] float

Description: 基于Verilog HDL的32位浮点运算加法器的源代码。-Based on the 32-bit floating point adder in Verilog HDL source code.
Platform: | Size: 1024 | Author: 朱文 | Hits:

Description: 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful implementation of the program the floating point adder.
Platform: | Size: 12144640 | Author: zhu yue | Hits:

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[Linux-Unix] fpadd

[VHDL-FPGA-Verilog] float

[VHDL-FPGA-Verilog] Float_add

[VHDL-FPGA-Verilog] adder

[Other] Fixed-Floating-Point-Adder-Multiplier-master

[VHDL-FPGA-Verilog] FP_adder

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