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[OS program] div2

Description: 大数除法的实现算法，不仅能实现两个大数的除法，而且能实现浮点数之间以及浮点数与整数之间的除法-majority of the division algorithm, is not only able to make large numbers of division two, but to achieve a float and between integer and floating point divider between the
Platform: | Size: 9257 | Author: 赵惠 | Hits:

[OS program] div2

Description: 大数除法的实现算法，不仅能实现两个大数的除法，而且能实现浮点数之间以及浮点数与整数之间的除法-majority of the division algorithm, is not only able to make large numbers of division two, but to achieve a float and between integer and floating point divider between the
Platform: | Size: 241664 | Author: 赵惠 | Hits:

[VHDL-FPGA-Verilog] 32divider

Description: 32位元2進位除法器 -32-bit binary divider 2
Platform: | Size: 2048 | Author: chen | Hits:

[VHDL-FPGA-Verilog] div(FLP)

Description: 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除-Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
Platform: | Size: 18432 | Author: TTJ | Hits:

[VHDL-FPGA-Verilog] juzhenqufaqi

Description: 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.
Platform: | Size: 6144 | Author: helinglin | Hits:

[Other] divider_latest.tar

Description: floating point divider
Platform: | Size: 5120 | Author: charanyakannan | Hits:

[VHDL-FPGA-Verilog] divider

Description: verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
Platform: | Size: 2048 | Author: 韩冰 | Hits:

[VHDL-FPGA-Verilog] immediate_float_divide_module

Description: 单精度浮点数除法器。用组合逻辑实现。高精度。-Single-precision floating point divider.
Platform: | Size: 2048 | Author: 张君 | Hits:

[Other] float-point-divider

Description: 基于FPGA的单精度浮点除法器vhdl设计程序,分模块程序。-FPGA-based single-precision floating point divider vhdl design program, sub module program.
Platform: | Size: 6144 | Author: 陈曦 | Hits:

[MPI] my_32fp_mult

Description: 这是一个计算32位浮点数的除法器，ALTERA的FPGA可直接用，用VHDL语言写的，希望能帮助有需要的朋友-This is a 32-bit floating-point calculation of divider, ALTERA FPGA can be directly used, written in VHDL language, hoping to help a friend in need
Platform: | Size: 3595264 | Author: jane | Hits:

[VHDL-FPGA-Verilog] FP_divider

Description: floating point divider for 32 bit with test bench
Platform: | Size: 11264 | Author: liki20 | Hits:

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