Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed. Platform: |
Size: 179200 |
Author:李中伟 |
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Description: 利用FPGA实现浮点运算的verilog代码
希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help Platform: |
Size: 130048 |
Author:jake |
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Description: This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.-This exercise will guide y ou through the step-by-step process of transfo rming a MATLAB floating-point model into a hard ware module that can be implemented in silicon ( FPGA or ASIC). The design is a general purpose FI R filter taken from the AccelDSP Examples direc tory. Platform: |
Size: 5120 |
Author:杨平 |
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Description: 经典的浮点运算VHDL源代码,是FPGA开发和VHDL学习的好资料!-Classical floating-point operations VHDL source code, is a FPGA and VHDL development of good information to learn! Platform: |
Size: 7168 |
Author:徐新风 |
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Description: 开发环境是FPGA开发工具，主要讲解用CPLD/FPGA实现浮点数的运算-Development environment is the FPGA development tools, primarily on the use of CPLD/FPGA to achieve floating-point arithmetic Platform: |
Size: 82944 |
Author:horse |
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Description: 用VHDL语言在CPLD／FPGA上实现浮点运算，资源多多共享,不亦乐乎!-VHDL language used in the CPLD/FPGA to achieve floating-point operations, resources, a lot of sharing, joy! Platform: |
Size: 145408 |
Author:wangzhe |
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Description: FPGA的PS2口接口程序，可识别PS2口键盘的输入-FPGA-PS2 port interface program to identify the mouth PS2 keyboard input Platform: |
Size: 665600 |
Author:冀少威 |
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Description: 高精度的浮点数除法运算，基于浮点运算的FPGA实现，单精度浮点数-High-precision floating-point division operation, the FPGA based on the realization of floating-point operations, single precision floating point Platform: |
Size: 81920 |
Author:jiachen |
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Description: 。本文针对三电平高压变频器控制要
求的特点，设计了基于DSP 和FPGA 的控制电路。利用DSP
进行高速浮点计算，满足实时控制的要求；FPGA 并行执行
程序，实现了多路触发信号的同时控制，而且由于采用了硬
件电路完成计算，提高了控制系统的可靠性-. In this paper, three-level voltage inverter control requirements of the features, design and FPGA-based DSP control circuit. High-speed floating-point calculations using DSP to meet the requirements of real-time control FPGA parallel implementation of the program, realized the trigger signal, while multi-channel control, and because use of the hardware circuitry to complete the calculation and improve the reliability of the control system Platform: |
Size: 320512 |
Author:scnu |
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Description: Taking Advantage of Advances in FPGA floating-Point IP cores -Taking Advantage of Advances in FPGA floating-Point IP cores Platform: |
Size: 485376 |
Author:andy |
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Description: 计算机里整数和小数形式就是按普通格式进行存储，例如1024、3.1415926等等，这个没什么特点，但是这样的数精度不高，表达也不够全面，为了能够有一种数的通用表示法，就发明了浮点数。
浮点数的表示形式有点像科学计数法（*.*****×10^***），它的表示形式是0.*****×10^***，在计算机中的形式为 .***** e ±***），其中前面的星号代表定点小数，也就是整数部分为0的纯小数，后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数，例如1024就能表示成0.1024×10^4，也就是 .1024e+004，3.1415926就能表示成0.31415926×10^1，也就是 .31415926e+001，这就是浮点数。浮点数进行的运算就是浮点运算。
浮点运算比常规运算更复杂，因此计算机进行浮点运算速度要比进行常规运算慢得多。(Floating point representation is a bit like scientific notation (*.***** * 10^***), its representation is 0.***** * 10^*** in the computer in the form of.***** e +, * * *) in front of the asterisk represents fixed-point decimal, which is part of the 0 pure decimal integer index, part of the back is a fixed integer. In this way, any integer and decimal can be expressed. For example, 1024 can be expressed as 0.1024 * 10^4, that is,.1024e+004, 3.1415926 can be expressed as 0.31415926 * 10^1, that is.31415926e+001, that is the floating point number. The operation of floating-point numbers is floating point operation.) Platform: |
Size: 130048 |
Author:哒啦啦啦 |
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Search - floating point fpga