Search - floating point verilog

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[VHDL-FPGA-Verilog] flowadd DL : 0: verilog编写的32位浮点加法器-32-bit Floating Point Addition Written in Verilog
Update : 2025-02-17 Size : 1kb Publisher : 张桓铭
[VHDL-FPGA-Verilog] fpu DL : 0: 利用FPGA实现浮点运算的verilog代码希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Update : 2025-02-17 Size : 127kb Publisher : jake
[Books] 32bits_float_muliplier DL : 0: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Update : 2025-02-17 Size : 95kb Publisher : downloader
[VHDL-FPGA-Verilog] MUL_Float_IEEE_754 DL : 0: IEEE754 floating point mul
Update : 2025-02-17 Size : 1kb Publisher : 洪瑞徽
[MPI] floatmul DL : 0: 采用VERILOG 语言进行设计实现32位浮点数乘法运算结果已经验证过放心使用-Verilog design language used to achieve 32-bit floating-point multiplication results have been verified ease of use
Update : 2025-02-17 Size : 1kb Publisher : NOVEI
[VHDL-FPGA-Verilog] flowadd DL : 0: 两个浮点数相加的加法器，使用verilog编写-Addition of two floating-point adder, the use of Verilog to prepare
Update : 2025-02-17 Size : 1kb Publisher : 蔡大
[VHDL-FPGA-Verilog] pi_ctrl DL : 0: VHDL实现PI调节的算法。内部使用整数计算，避开了浮点数的运算。仿真结果正确-VHDL realize PI regulator algorithm. Internal use integer calculations to avoid the floating point arithmetic. The simulation results correctly
Update : 2025-02-17 Size : 1kb Publisher : 刘新
[VHDL-FPGA-Verilog] fadd DL : 0: 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard
Update : 2025-02-17 Size : 2kb Publisher : 兰兰
[Algorithm] multiply DL : 0: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Update : 2025-02-17 Size : 4kb Publisher : lanty
[Linux-Unix] fpadd DL : 0: 利用verilog hdl编写的浮点加法器运算单元，单精度。-Verilog hdl prepared to use floating-point adder computing unit, single-precision.
Update : 2025-02-17 Size : 12kb Publisher : 孟军
[VHDL-FPGA-Verilog] undistort DL : 0: floating point arthematic function with verilog code
Update : 2025-02-17 Size : 496kb Publisher : tragun
[VHDL-FPGA-Verilog] 69491706fp_add_sub DL : 0: verilog code for floating point adding
Update : 2025-02-17 Size : 671kb Publisher : bin
[VHDL-FPGA-Verilog] fpu100_latest.tar DL : 1: 这是一个32位的浮点运算单元（FPU），它可以根据IEEE754标准被完全编译。此FPU已被硬件测试和被软件仿真通过。-This is a 32-bit floating point unit (FPU),It can do arithmetic operations on floating point numbers. The FPU complies fully with the IEEE 754 Standard. The FPU was tested and simulated in hardware and software.
Update : 2025-02-17 Size : 1.89mb Publisher : 赵恒
[VHDL-FPGA-Verilog] floating_point_addition_subtraction DL : 0: Simple floating point addition unit written in Verilog
Update : 2025-02-17 Size : 3kb Publisher : binh
[VHDL-FPGA-Verilog] Floating-Point-Adder DL : 0: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Update : 2025-02-17 Size : 151kb Publisher : 凌音
[VHDL-FPGA-Verilog] floating-point-adder DL : 0: verilog implementation of the floating point adder
Update : 2025-02-17 Size : 2kb Publisher : ramtin
[VHDL-FPGA-Verilog] floating-point-multiplier DL : 0: verilog implementation of the floating point multiplier
Update : 2025-02-17 Size : 1kb Publisher : ramtin
[VHDL-FPGA-Verilog] sqrt_for_single_float_point DL : 0: 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
Update : 2025-02-17 Size : 5kb Publisher : 楚艳超
[VHDL-FPGA-Verilog] subtraction floating point DL : 0: subtract two number floating point (32 bit)
Update : 2025-02-17 Size : 354kb Publisher : truong tho
[Other] Fixed-Floating-Point-Adder-Multiplier-master DL : 0: Fixed-Floating-Point-Adder-Multiplier with test bench
Update : 2025-02-17 Size : 9kb Publisher : liki20

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