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[
VHDL-FPGA-Verilog
]
DIGTAL_FIR
Description:
环路滤波器的设计，基于FPGA的锁相环应用。-Loop filter design, FPGA-based PLL applications.
Platform:
|
Size:
774144
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Author:
梁大法
|
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Search - for loop in vhdl for fir
Search - for loop in vhdl for fir