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[Other Embeded program] 完整verilog学习代码

Description: 完整verilog学习代码，
Platform: | Size: 2291669 | Author: wjwqbit@ | Hits:

[VHDL-FPGA-Verilog] FPGA-verilog-交通灯

Description: 采用verilog编写的代码，用FPGA实现交通灯控制，包含有数码管显示控制，倒计时控制，状态机等，是练习Verilog代码编写的一个很好的实例！
Platform: | Size: 2142 | Author: hangman_102@126.com | Hits:

[VHDL-FPGA-Verilog] FPGA控制VGA显示（Verilog）

Description: 用FPGA开发板控制VGA显示，以800*600的分辨率，首先在屏幕的正中央依次出现“新”“年”“快”“乐”四个汉字，并分别移动到屏幕的四个角落，接着在屏幕中部从左至右依次出现“Happy New Year”英文字样，然后出现三个由小到大再消失的圆形图标模拟烟花，最后在黑屏中闪烁金星。字体均采用不同颜色，增添喜庆气氛。 本代码是练习VGA控制，ROM调用，时序控制及状态机运用的一个综合实例！
Platform: | Size: 11611 | Author: hangman_102@126.com | Hits:

[SourceCode] FPGA VERILOG

Description: fpga VERILOG
Platform: | Size: 2571364 | Author: chch1010 | Hits:

[Books] ]FPGA设计指导手册PDF版

Description: FPGA设计指导手册PDF版 将如何设计fpga的,考虑了一些FGPA的关键问题可以参考一下 对初学者有帮助的-FPGA design instruction manual PDF version of the design they simply consider the FGPA some of the key issues for reference to help beginners
Platform: | Size: 260096 | Author: 沉沉 | Hits:

[VHDL-FPGA-Verilog] 能综合的YCrCb2RGB模块（verilog)_采用3级流水线

Description: 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
Platform: | Size: 1024 | Author: 于飞 | Hits:

[Other Embeded program] CAN协议控制器的Verilog实现

Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Platform: | Size: 38912 | Author: wl | Hits:

[VHDL-FPGA-Verilog] qep_data_bus

Description: 基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的-address bus interface based on the four frequency signal encoder interface FPGA Verilog HDL
Platform: | Size: 1187840 | Author: 孙卓君 | Hits:

[Other] Altera-FPGA-Guide

Description: Altera FPGA 的开发工具的详细教程，有例程与步奏-Altera FPGA development tools detailed guidance, routines and step-outs
Platform: | Size: 685056 | Author: yxc | Hits:

[SCM] FPGA--DDS-PhaseMeasure

Description: Verilog实现的DDS正弦信号发生器和测频测相模块，DDS模块可产生两路频率和相位差均可预置调整的值正弦波，频率范围为20Hz-5MHz，相位范围为0°-359°，测量的数据通过引脚传输给单片机，单片机进行计算和显示。-Verilog realize the DDS sine wave signal generator and frequency measurement module test phase, DDS module can generate both frequency and phase difference can be preset to adjust the value of sine wave, frequency range of 20Hz-5MHz, phase range of 0 °-359 ° , measurement data and transmit them to the single-chip pin, single-chip microcomputer to calculate and display.
Platform: | Size: 1371136 | Author: haoren | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: FPGA verilog，比较好的verilog源码，现提供给大家，供参考-FPGA verilog, better Verilog source code is now available to everyone, for reference
Platform: | Size: 41984 | Author: leedong | Hits:

[VHDL-FPGA-Verilog] fpga

Description: fpga功能实现有限字长响应FIR 用verilog编写-FPGA functionality in response to the realization of finite word-length FIR prepared using Verilog
Platform: | Size: 139264 | Author: 吴务 | Hits:

[VHDL-FPGA-Verilog] FPGA_two-way_IO

Description: FPGA Verilog,双向端口的研究,比较全,由ASSIGN和ALWAYS模块组成,测试可用-FPGA Verilog, bi-directional port studies comparing full-, and ALWAYS by ASSIGN modules, testing available
Platform: | Size: 115712 | Author: 鲍纯贝 | Hits:

[VHDL-FPGA-Verilog] fpga-2

Description: 这是我写的一个关于fpga verilog的程序希望有对初学着有帮助
Platform: | Size: 103424 | Author: 甘同同 | Hits:

[VHDL-FPGA-Verilog] fpga-jpeg

Description: jepg verilog example
Platform: | Size: 103424 | Author: 展望 | Hits:

[VHDL-FPGA-Verilog] fpga

Description: Verilog HDl代码，学习一颗看一下-Verilog HDl code, learning to look at a
Platform: | Size: 1449984 | Author: 魏杰 | Hits:

[VHDL-FPGA-Verilog] AD9229-FPGA-files

Description: adi串行AD AD9229的控制使用ISE平台 Verilog语言 -adi serial ADAD9229 control the use of ISE platform Verilog language
Platform: | Size: 184320 | Author: 徐凯 | Hits:

[Other] VerilogHDL-FPGA

Description: Verilog HDL程序设计实例详解 光盘 FPGA-Verilog HDL programming example explanation of CD-ROM
Platform: | Size: 19944448 | Author: 蔡新林 | Hits:

[VHDL-FPGA-Verilog] FPGA-verilog

Description: 用Verilog语言编写的一些简单的FPGA入门实验，用ALTERA DE2开发板和Quartus_II软件开发环境。包括：流水灯实验、数码管显示实验-With Verilog language preparation some simple introduction experiment, with FPGA ALTERA DE2 development board and Quartus_II software development environment. Include water lamp experiment, digital pipe display experimentation, etc
Platform: | Size: 10240 | Author: 星光依旧 | Hits:

[VHDL-FPGA-Verilog] Verilog HDL Practice

Description: FPGA Verilog HDL程序设计练习进阶，实用的FPGA学习资料。(Practicing of FPGA Verilog HDLprogramming)
Platform: | Size: 376832 | Author: ts_ear | Hits:
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