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[Other resource] AD9229-FPGA-files

Description: adi串行AD AD9229的控制使用ISE平台 Verilog语言
Platform: | Size: 185028 | Author: 徐凯 | Hits:

[Software Engineering] huawei

Description: 华为FPGA设计流程指南，FPGA设计者、项目管理者必读的文档，看看别人是怎么做的。-Huawei FPGA design flow guide, FPGA designers, project managers must-read documents, take a look at how others do.
Platform: | Size: 31744 | Author: 贺雷 | Hits:

[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
Platform: | Size: 163840 | Author: xiaozhu | Hits:

[VHDL-FPGA-Verilog] AD9229-FPGA-files

Description: adi串行AD AD9229的控制使用ISE平台 Verilog语言 -adi serial ADAD9229 control the use of ISE platform Verilog language
Platform: | Size: 184320 | Author: 徐凯 | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] ASYNCFIFO

Description: 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
Platform: | Size: 75776 | Author: Denny | Hits:

[VHDL-FPGA-Verilog] USB

Description: Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be
Platform: | Size: 140288 | Author: Roy | Hits:

[VHDL-FPGA-Verilog] SwitchLed

Description: FPGA入门程序。适合编程初学者的学习。由开关控制LED灯的亮灭。ISE集成开发环境。Verilog HDL语言编写-FPGA entry procedures. Programming for beginners to learn. LED lights from the light switch control off. ISE Integrated Development Environment. Language Verilog HDL
Platform: | Size: 244736 | Author: 李海波 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Platform: | Size: 179200 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] fpga-fir

Description: xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
Platform: | Size: 1006592 | Author: bambod | Hits:

[VHDL-FPGA-Verilog] Verilog HDL program

Description: 文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and contains a large number of examples, as well as source code)
Platform: | Size: 11567104 | Author: 没伞的孩子 | Hits:

[VHDL-FPGA-Verilog] parallel_norflash_test

Description: ISE工程，并行nor flash的读、写、擦出，其中有个调用FIFO16-16的IP核，已经在工程中(ISE engineering, parallel nor FLASH read, write, erase, where there is a call FIFO16-16 IP core, has been in the project)
Platform: | Size: 1124352 | Author: 张超 | Hits:

[Communication-Mobile] RISC_CPU完整代码

Description: 硬件实现一个完整的CPU，利用verilog编写，可在ISE上直接使用(Hardware implements a full CPU)
Platform: | Size: 3099648 | Author: TJUWUCK | Hits:

[VHDL-FPGA-Verilog] eeprom_test_Verilog

Description: eeprom工程，实现了基本的读写，供参考。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置和逻辑可控制。(EEPROM project, the realization of the basic reading and writing for reference. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify pin configuration and logic control according to its own hardware.)
Platform: | Size: 159744 | Author: shaoyang_v | Hits:

[VHDL-FPGA-Verilog] uart_test_Verilog

Description: 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configuration according to its own hardware.)
Platform: | Size: 128000 | Author: shaoyang_v | Hits:

[VHDL-FPGA-Verilog] 图像中值滤波FPGA实现V1.0

Description: 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
Platform: | Size: 30031872 | Author: gxgone | Hits:

[VHDL-FPGA-Verilog] lmf

Description: 在ISE下，FPGA产生线性调频信号，并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)
Platform: | Size: 1484800 | Author: QAQ取啥啥不行 | Hits:

[VHDL-FPGA-Verilog] 好-无线通信FPGA设计-Xilinx

Description: 《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless communication FPGA is based on the development platform of Xilinx's FPGA and combines the two directions of FPGA and wireless communication technology. Through a large number of examples of FPGA development, the principle and implementation process of common modules in wireless communication are described in detail, including the basis of digital signal processing, digital filter and multi-rate signal. Processing, digital modulation and demodulation, channel coding, system synchronization, adaptive filtering algorithm, optimal receiver, and key technologies of WCDMA system. The concept of Wireless Communication FPGA Design is clear, and the idea is clear. It pursues comprehensiveness, system and practicality, so that readers can have the ability to develop FPGA in the field of wireless communication in a relatively short time.)
Platform: | Size: 11018240 | Author: 无线电之家99 | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 先用Matlab理论仿真，得出滤波器系数。再用Verilog语言在ISE环境下编写程序，通过Modelsim和ChipScope进行波形仿真和引号抓取，从而提高调试的效率。通过手机发送指令来控制上下变频器的参数。(Firstly, the filter coefficients are obtained by simulation with the theory of matlab. Then the program is written in Verilog language under ISE environment. Waveform simulation and quotation mark grabbing are carried out through Modelsim and ChipScope, so as to improve the efficiency of debugging. The parameters of up-down converter are controlled by sending instructions from mobile phone.)
Platform: | Size: 6740992 | Author: 财哥在此 | Hits:

[VHDL-FPGA-Verilog] sram_ctr

Description: SRAM VERILOG 实现FPGA控制SRAM的功能。测试可以使用。(SRAM verilog fpga vivado ise quartus.)
Platform: | Size: 1024 | Author: hwz | Hits:
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