Search - fpga NCO

Search - fpga NCO - List

[Other resource] CORDIC_mixer DL : 1: FPGA可实现的，使用cordic算法的NCO模块混频模块。该模块基于cordic原理，算法中只需要加法和移位运算既可以完成信号的混频功能-FPGA can be achieved, the use of the NCO cordic algorithm module mixing module. Cordic module based on the principle, the algorithm only needs Adder and shift operator can complete signal mixing function
Update : 2008-10-13 Size : 853byte Publisher : rossi
[Other resource] NCO_sin DL : 0: 基于FPGA的NCO设计,采用查表方法.八位地址线,一个周期采点256个,输出八位数据.
Update : 2008-10-13 Size : 4.04kb Publisher : wei
[matlab] CORDIC_mixer DL : 0: FPGA可实现的，使用cordic算法的NCO模块混频模块。该模块基于cordic原理，算法中只需要加法和移位运算既可以完成信号的混频功能-FPGA can be achieved, the use of the NCO cordic algorithm module mixing module. Cordic module based on the principle, the algorithm only needs Adder and shift operator can complete signal mixing function
Update : 2025-02-17 Size : 1kb Publisher : rossi
[GPS develop] GPS_code_nco DL : 0: 这是GPS接收机，基带处理模块中累加模块设计代码，用于码跟踪环。代码设计巧妙，避免了消耗FPGA中比较稀缺的硬件乘法器资源。-This is the GPS receiver, Baseband Processing Module cumulative module design code for the code tracking loop. Code so cleverly designed to avoid the consumption of more FPGA hardware multiplier scarce resources.
Update : 2025-02-17 Size : 2kb Publisher : 吴飞
[VHDL-FPGA-Verilog] NCO_sin DL : 0: 基于FPGA的NCO设计,采用查表方法.八位地址线,一个周期采点256个,输出八位数据.-NCO of the FPGA-based design, using look-up table method. 8 address lines, a cycle of mining point 256, the output data 8.
Update : 2025-02-17 Size : 4kb Publisher : wei
[VHDL-FPGA-Verilog] dds_new DL : 0: 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级-Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
Update : 2025-02-17 Size : 1.93mb Publisher : 李春剑
[VHDL-FPGA-Verilog] NCO DL : 0: 基于FPGA和SRAM的数控振荡器的设计与实现-SRAM-based FPGA and NCO of the design and implementation
Update : 2025-02-17 Size : 44kb Publisher : gsg
[Other] 11 DL : 0: NCO 在信号处理方面有着广泛的应用。而函数发生器是NCO 中的关键部分，本文基于FPGA 用状态机和流水线方法实现了CORDIC 算法，并取代了传统的ROM 查找表法。最后通过Quartus II 软件给出仿真结果，验证了理论的正确性。-NCO in the Signal Processing has a wide range of applications. The function generator is a critical part of NCO, the paper-based FPGA using state machine implementation of the Ways and pipelining CORDIC algorithm, and replaces the traditional ROM look-up table method. Finally through the Quartus II software give simulation results to verify the correctness of the theory.
Update : 2025-02-17 Size : 161kb Publisher : LEO
[VHDL-FPGA-Verilog] RealizationofdigitaldownconversionbyFPGA DL : 0: 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the preparation of some call a combination of IP core method of the FPGA digital down conversion method, and completed its main modules of simulation and debugging, and initial system-level verification.
Update : 2025-02-17 Size : 159kb Publisher : 于银
[DSP program] dspddc_R12p1 DL : 1: 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
Update : 2025-02-17 Size : 17kb Publisher : 郑程
[Other] CarrierGen DL : 0: 用VC的程序的方法来模拟FPGA的NCO的功能-Program with VC methods to simulate the function of FPGA-NCO
Update : 2025-02-17 Size : 1kb Publisher : dgq
[Software Engineering] ddc DL : 0: 电子科大2009-数字中频技术的研究与FPGA实现，主要是DDC的FPGA实现，NCO部分的FPGA实现！-UESTC 2009- Digital IF Research and FPGA, the FPGA implementation is mainly DDC, NCO segment FPGA to achieve!
Update : 2025-02-17 Size : 5.58mb Publisher : peter
[VHDL-FPGA-Verilog] A_digital_WaveformGenerator_and_Oscilloscope_based DL : 0: 一种基于BASYS开发板(Xilinx Spartan-3E FPGA)的波形发生器和示波器的设计，可以产生多种可调波形，并实时显示在电脑显示器或者投影仪上。波形发生器采用基于ROM的数字控制振荡器（NCO）实现，示波器采用VGA接口实时显示。-A kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.This design can make adjustable sine,triangle and rectangle waveform.It also can show the waveform real time on a computer dispaly or a projecting apparatus via a VGA cable.The emphases of this project is to realize real-time VGA interface in a FPGA.
Update : 2025-02-17 Size : 3.26mb Publisher : 张文
[VHDL-FPGA-Verilog] cordic DL : 0: FPGA中数字信号发生器NCO用CORDIC实现产生正弦余弦-failed to translate
Update : 2025-02-17 Size : 2kb Publisher : lilun
[VHDL-FPGA-Verilog] NCO DL : 0: 关于FPGA设计实现NCO，包括查找表法和CORDIC算法的改进-FPGA design and implementation on the NCO, including the look-up table method and the CORDIC Algorithm
Update : 2025-02-17 Size : 1.38mb Publisher : 张子龙
[VHDL-FPGA-Verilog] NCO DL : 0: 基于FPGA的NCO数字化实现方法,并从原理上作了必要的分析-NCO of digital FPGA-based implementation, and made from the principle of the necessary analysis
Update : 2025-02-17 Size : 182kb Publisher : fy
[VHDL-FPGA-Verilog] nco DL : 0: 基于FPGA的压控震荡器，可以通过震荡器来对输入信号进行有效的分频，而且是任意的分频系数都可以-FPGA-based VCO oscillator input signal, the effective frequency division and any sub-frequency coefficients can be
Update : 2025-02-17 Size : 3.09mb Publisher : zhou
[VHDL-FPGA-Verilog] NCO DL : 0: 基于FPGA的DDS设计，通过外接DA转换器输出稳定的正弦波，方波和三角波，可单独产生时钟，不必借助硬件连接，包含寄存器程序，累加器程序和时钟发生电路等，以及顶层设计原理图-The DDS FPGA-based design, through an external DA converter output stable sine wave, square wave and triangular wave, can produce a single clock, without the help of the hardware connection, including the register program, accumulator program and a clock generation circuit, and a top design schematics
Update : 2025-02-17 Size : 5.56mb Publisher : 孙雨晗
[Communication-Mobile] NCO DL : 0: 一种基于FPGA的数控振荡器技术的实现方法(FPGA implementation of NC oscillator NCO)
Update : 2025-02-17 Size : 1.68mb Publisher : 哈迪
[VHDL-FPGA-Verilog] nco1mhz DL : 0: 使用FPGA元件中的NCO产生1MHZ频率\相位可调的输出(Use the NCO in the FPGA element to produce 1MHZ frequency \ phase adjustable output)
Update : 2025-02-17 Size : 2kb Publisher : SMALLMOON

« 12 »