Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fpga capture

Search list

[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
Platform: | Size: 163840 | Author: xiaozhu | Hits:

[Software Engineering] up_261128143F5F01A9

Description: 为解决直接序列扩频系统的数字收发机中初始频率的捕获问题，提出了一种通过DFT变换，在频域 上进行抛物插值运算的频偏估计的算法。该算法可适应低信噪比、宽频率偏移范围的恶劣通信环境和突发的通信 模式，且算法复杂度较低。该算法已在FPGA 中实现。-To address the direct sequence spread spectrum system, the number of transceivers in the initial frequency of the capture problem, a transformation through the DFT, in the frequency domain for parabolic interpolation computing frequency offset estimation algorithms. The algorithm can be adapted to low signal to noise ratio, broadband rates offset the scope of bad communications environment and unexpected modes of communication, and the algorithm complexity low. The algorithm has been realized in the FPGA.
Platform: | Size: 63488 | Author: 赵平 | Hits:

[GPS develop] GPStracking

Description: GPS信号基带处理中频信号的跟踪捕获方面IEEE文章-GPS baseband signal IF signal tracking to capture aspects of IEEE article
Platform: | Size: 165888 | Author: 刘旭东 | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[GPS develop] code_dco

Description: 通信电路中产生扩频码的电路，应用于GPS中的跟踪和捕获．-Communication circuit of the circuit generated spreading codes used in GPS tracking and capture.
Platform: | Size: 1024 | Author: Li Gengmin | Hits:

[VHDL-FPGA-Verilog] RS232capture

Description: This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file do it.
Platform: | Size: 39936 | Author: Joelmir J Lopes | Hits:

[Communication] AnFPGASoftwareDefinedUltraWidebandTransceiver

Description: Increasing interest in ultra-wideband (UWB) communications has engendered the need for a test bed for UWB systems. An FPGA-based software-defined radio provides both postfabrication definition of the radio and ample parallel processing power. This thesis presents the FPGA design for a software-defined radio targeted to impulse ultra-wideband signals. The system is capable of an effective sampling frequency of up to 8 G-samples/s using timeinterleaved sampling with eight 1-GHz ADCs. The system is also capable of transmitting UWB pulses using a transmitter board controlled by the FPGA. In this thesis, the FPGA design used to capture and export data from the eight ADCs is presented, along with two systems which make use of the transceiver: a pilot-based matched filter communications system, and a remote vital signs monitor.
Platform: | Size: 1396736 | Author: chaiwat | Hits:

[Special Effects] VIDEO-FPGA

Description: 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
Platform: | Size: 6034432 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] 61EDA

Description: 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌 入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案， 针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a variety of video capture programs reviewed. On how to use CCD camera capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system realization method was studied. Used to camera mode+ decoder chip collection program for video decoder chip ADV7181B, realized the I2C bus configuration, ITU656 decoder, VGA display module design. The video capture controller has been designed in the Altera' s CycloneII series FPGA (EP2C35) to achieve. The results showed that this design has a high speed, low cost, easy to integrate the advantages of
Platform: | Size: 179200 | Author: 李明 | Hits:

[Video Capture] sram_saa1117verilog

Description: 图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过-Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by
Platform: | Size: 25600 | Author: 蹇清平 | Hits:

[Other] deep_LabVIEW_FPGA

Description: NI 通过LabVIEW FPGA 模块和可重复配置I/O(RIO)硬件设备，为测量和控制系统中整合FPGA 技术的 灵活性提供了直观且现成可用的解决方案。您可以使用LabVIEW图形化编程定义FPGA 芯片上的逻辑 功能，您不需要任何的有关底层硬件描述语言(HDLs)的知识，如VHDL 或是Verilog，也不需要了解板 卡级硬件设计，就可以将FPGA 芯片嵌入到NI 可重复配置I/O 系列硬件目标当中。另外，LabVIEW还 可以让您轻松地集成图象采集/分析、运动控制，以及CAN 和RS232 等工业通信功能。-Through the LabVIEW FPGA Module and NI reconfigurable I/O (RIO) hardware device, for measurement and control systems integrate the flexibility of FPGA technology provides the intuitive and readily available solution. You can use the LabVIEW graphical programming custom FPGA logic functions on a chip, you do not need any of the underlying hardware description languages (HDLs) knowledge, such as VHDL or Verilog, do not need to understand the board-level hardware design, it can be FPGA chip embedded into the NI reconfigurable I/O family of hardware Goals. In addition, LabVIEW also allows you to easily integrate image capture/analysis, motion control, as well as CAN and RS232 communication industries.
Platform: | Size: 274432 | Author: 侯yl | Hits:

[VHDL-FPGA-Verilog] dmfilter

Description: gps接收机伪码捕获时采用的匹配滤波器，能完成接收码的捕获。-gps receiver pseudo-code used to capture the matched filter, receiving yards to complete the capture.
Platform: | Size: 1024 | Author: 易凯 | Hits:

[Other] videocaptureandtransmissonbasedonfpga

Description: 用FPGA实现视频采集与传输的原理与部分代码。-FPGA implementation using video capture and transmission of the principle and part of the code.
Platform: | Size: 6177792 | Author: FEYNMAN | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 基于FPGA哥专用芯片双核心处理，MB86S02 CMOS 视频采集实现嵌入式视频采集与处理的设计过程-FPGA-based ASIC dual-core processing Colombia, MB86S02 CMOS video capture video capture and processing of embedded design process
Platform: | Size: 5120 | Author: 周志法 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s internal logic to realize the ADC, SDRAM, LAN controller chip DM9000 timing control to capture FPGA as the core of the system, through the ADC, will be collected The data stored in SDRAM, the SDRAM in order to read data from the FIFO method, and data results to a computer via Ethernet interface
Platform: | Size: 388096 | Author: gdr | Hits:

[VHDL-FPGA-Verilog] the-capture-of-the-camera

Description: 用FPGA来实现摄像头的捕捉和采集，源代码-FPGA to implement the capture and collection of the camera
Platform: | Size: 243712 | Author: 初昀 | Hits:

[Program doc] OFDM-FPGA

Description: 频率同步是宽带OFDM系统中的关键技术，IEEE 802.11a 采用OFDM技术，利用其前导序列的重复结构，提出了一种分步的粗细频偏捕获与校正算法，同时为了补偿时域同步后的残余相差和适应信道的时变特性，还提出了一种基于频域导频的相位跟踪方案-Frequency synchronization is a key technology in the broadband OFDM systems, IEEE 802.11a uses OFDM technology, the use of the repetitive structure of the leader sequence, the thickness of a step frequency offset capture and correction algorithm, when the order to compensate at the same time domain synchronous residualthe difference between and adapt to the time-varying characteristics of the channel is also proposed based on frequency domain pilot phase tracking scheme
Platform: | Size: 858112 | Author: Chaos | Hits:

[Program doc] carrier-frequency--capture

Description: 高动态环境下载波频率捕获的设计与实现，针对高动态的机载环境和FPGA的应用要求，比较并确定了基于软件无线电思想的扩频接收机中载波频率捕获的方案；完成了鉴频器、比特定时提取电路等模块的设计.论文对系统进行了理论分析和性能仿真-Download frequency of the high dynamic environment to capture the design and implementation of application requirements for high dynamic airborne environment and FPGA, compare and determine based on the ideas of software radio spread spectrum receiver carrier frequency capture program the completion of a frequency discriminator bit timing extraction circuit module design thesis on the system of theoretical analysis and performance simulation
Platform: | Size: 1920000 | Author: jing | Hits:

[VHDL-FPGA-Verilog] FPGA-SRC

Description: 用于DSP+FPGA开发系统，可用于采集一帧图像并控制SRAM、SDRAM数据存取。-Used in DSP+ FPGA development system, to capture an image and control the SRAM, SDRAM data access.
Platform: | Size: 2826240 | Author: 李雷 | Hits:

[Software Engineering] FPGA-based-clock-extraction-circuit

Description: 基于FPGA的时钟提取电路.跳变沿捕捉程序.可控计数器程序-FPGA-based clock extraction circuit. Edge capture process. Controllable counter program
Platform: | Size: 404480 | Author: 张成良 | Hits:
« 12 3 4 »

CodeBus www.codebus.net