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[VHDL-FPGA-Verilog] EDA

Description: 里面是一个FIR滤波器的设计报告 里面有具体的 代码 等等 加法器 乘法器 见发起 等等 承平-There is a FIR filter design report there are specific code adder multiplier, etc., etc., see Cheng-Ping initiated
Platform: | Size: 189440 | Author: 丛宇 | Hits:

[VHDL-FPGA-Verilog] chengxu

Description: 信号测量 实时显示 延时2秒 键盘扫描-Signal measurement in real-time display the keyboard scanning delay 2 seconds
Platform: | Size: 25600 | Author: 丁涛 | Hits:

[DSP program] stream

Description: 实验简介： 本程序 主要在于了解用FPGA控制数据的基本方法。-Experiment Description: ben cheng xu key is to understand the FPGA control data using the basic method.
Platform: | Size: 3072 | Author: 军军 | Hits:

[VHDL-FPGA-Verilog] jing-dain--FPGA-cheng-xu

Description: 关于FPGA的经典算法，包括数码管的编程和显示，用Verilog HDL语言写的程序，在开发板上已经测试成功！-Classical algorithm on the FPGA, including digital programming and display, using Verilog HDL language to write programs, the development board has been tested successfully!
Platform: | Size: 514048 | Author: chenfeihu | Hits:

[VHDL-FPGA-Verilog] CHENG

Description: 这是关于psk解调与调制器的VHDL语言的程序 是关于FPGA的实现，希望能帮助各位-This is about psk demodulator and modulator VHDL language program is implemented on the FPGA, hoping to help you
Platform: | Size: 2048 | Author: 李淼 | Hits:

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