Description: FPGA/keyboard interface is shown in figure 1. When the FPGA “reads” the Data or
Clock inputs both PS2Data_out and PS2Clk_out are kept low which puts the tri-state buffers
in high impedance mode. When the FPGA "writes" a logic 0 on an output, the corresponding
x_out (x = PS2Data or PS2Clk) signal is set high which pulls the line low. When “writing”
logic 1 the FPGA simply sets the x_out signal low. Platform: |
Size: 432128 |
Author:qweqweqwe |
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Description: 主要介绍VHDL下,电子时钟、LCD、LED、电子琴,电梯等开发程序。-Introduces the VHDL, the electronic clock, LCD, LED, keyboard, elevator and other development programs. Platform: |
Size: 13878272 |
Author:huizeng |
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Description: 对sparten 3E fpga的板子的一个各个功能模块的多功能vhdl程序,包括键盘防抖,数字时钟等-Sparten 3E fpga of the board of a multi-purpose function modules vhdl procedures, including keyboard, image stabilization, digital clock, etc. Platform: |
Size: 2060288 |
Author:邓民明 |
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Description: FPGA平台下基于Nios II的数字闹钟的源程序,从DS1302读取时钟数据,在LCD12864上显示出来,按键控制闹钟设定,蜂鸣器闹铃。-Digital clock Nios II source program based on the FPGA platform, clock read data from the DS1302, in the LCD12864 display, keyboard control alarm, buzzer alarm. Platform: |
Size: 12622848 |
Author:光速不变 |
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Description: 基于altera FPGA的多功能数字钟程序,但是不是简单的数字钟,还支持VGA图形化钟表显示,并且有鼠标,键盘,温度显示等等功能。-Altera FPGA based multi-functional digital clock program, but not a simple digital clock, timepiece also supports VGA graphics display, and there is a mouse, keyboard, temperature display and more. Platform: |
Size: 203776 |
Author:周成 |
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Description: 闹钟
工程说明
本工程包括矩阵键盘和数码管显示模块,共同实现一个带有闹钟功能、可设置时间的数字时钟。
案例补充说明
我们通过建立四个清晰直观的模块(数码管显示模块,矩阵键盘扫描模块,时钟计数模块,闹钟设定模块),以及建立完善的信号列表和运用verilog语言编写简洁流畅的代码,实现电子闹钟时、分、秒计时以及设置、修改、重置等功能。(alarm clock
Engineering description
This project includes matrix keyboard and digital display module, together with a digital clock with alarm clock function and set time.
Case Supplement
We build four clear and intuitive module (digital display module, matrix keyboard scanning module, clock counting module, alarm clock module), and establish and perfect the code signal list using Verilog language is concise and fluent, electronic clock, minutes and seconds, setting, modify, reset and other functions.) Platform: |
Size: 174080 |
Author:明德扬科教
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